Patents by Inventor Kai-Yu Yang
Kai-Yu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145596Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.Type: ApplicationFiled: January 2, 2024Publication date: May 2, 2024Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang, Meng-Han Chou
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Publication number: 20240138059Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.Type: ApplicationFiled: November 23, 2022Publication date: April 25, 2024Applicant: Unimicron Technology Corp.Inventors: Kai-Ming Yang, Chia-Yu Peng, Cheng-Ta Ko, Pu-Ju Lin
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Publication number: 20240138063Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.Type: ApplicationFiled: November 15, 2022Publication date: April 25, 2024Applicant: Unimicron Technology Corp.Inventors: Ping-Tsung Lin, Kai-Ming Yang, Chia-Yu Peng, Pu-Ju Lin, Cheng-Ta Ko
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Publication number: 20240105850Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.Type: ApplicationFiled: November 28, 2023Publication date: March 28, 2024Inventors: Che-Yu Yang, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng
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Patent number: 11943877Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.Type: GrantFiled: March 2, 2022Date of Patent: March 26, 2024Assignee: Unimicron Technology Corp.Inventors: Wen-Yu Lin, Kai-Ming Yang, Chen-Hao Lin, Pu-Ju Lin, Cheng-Ta Ko, Chin-Sheng Wang, Guang-Hwa Ma, Tzyy-Jang Tseng
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Publication number: 20240097011Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITEDInventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
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Patent number: 11923457Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.Type: GrantFiled: June 27, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Che-Yu Yang, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng
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Patent number: 10305792Abstract: A network detection method links multiple nodes residing in a network topology to form multiple edges and creates snake paths through the edges using a snake algorithm. The routing frequencies of each of the snake paths is calculated, and software-defined network (SDN) policy flows to each of the nodes are produced and applied. The health and performance status, and available bandwidths, of the snake paths are dynamically detected via packet flows using a pathChirp bandwidth detection method.Type: GrantFiled: March 18, 2016Date of Patent: May 28, 2019Assignee: Cloud Network Technology Singapore Pte. Ltd.Inventors: Kai-Yu Yang, Bo-Run Shao, Hao-Wen Chung
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Publication number: 20180183799Abstract: A system for defending against malicious website includes an intelligent module and a deploying module. The intelligent module collects and stores information as to malicious website from third-party trusted websites. The malicious website is rated for risk and a malicious website having a high risk is preset as a dangerous website, and a deploying signal is sent after the preset dangerous website is set. The deploying module adds the dangerous website information preset dangerous website to a flow table and deploys the flow table to a plurality of OpenFlow (OF) switch. An OF switch can detect whether a browsing website to be opened by a user is recorded in the flow table, and if so, the OF switch blocks the browsing of such website. A method for defending against malicious website is also disclosed.Type: ApplicationFiled: December 28, 2016Publication date: June 28, 2018Inventor: KAI-YU YANG
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Patent number: 9584572Abstract: A cloud service device includes a data center that stores video preview images. A first message requesting previewing multiple images from is received from a multimedia device. Multiple offsets corresponding to the multiple images according to the first time interval and the first image number are calculated and time points corresponding to the multiple images according to the multiple offsets and the first preview time point are calculated. The multiple images from the data center according to the calculated time points are obtained and transmitted to the multimedia device to preview.Type: GrantFiled: January 8, 2014Date of Patent: February 28, 2017Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: Kai-Yu Yang
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Publication number: 20160337188Abstract: A network detection method links multiple nodes residing in a network topology to form multiple edges and creates snake paths through the edges using a snake algorithm. The routing frequencies of each of the snake paths is calculated, and software-defined network (SDN) policy flows to each of the nodes are produced and applied. The health and performance status, and available bandwidths, of the snake paths are dynamically detected via packet flows using a pathChirp bandwidth detection method.Type: ApplicationFiled: March 18, 2016Publication date: November 17, 2016Inventors: KAI-YU YANG, BO-RUN SHAO, HAO-WEN CHUNG
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Publication number: 20140289310Abstract: A cloud service device includes a data center that stores video preview images. A first message requesting previewing multiple images from is received from a multimedia device. Multiple offsets corresponding to the multiple images according to the first time interval and the first image number are calculated and time points corresponding to the multiple images according to the multiple offsets and the first preview time point are calculated. The multiple images from the data center according to the calculated time points are obtained and transmitted to the multimedia device to preview.Type: ApplicationFiled: January 8, 2014Publication date: September 25, 2014Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: KAI-YU YANG
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Patent number: 8248937Abstract: A packet forwarding device stores a predetermined threshold and a predetermined condition value of a first wide area network (WAN) port, and forwards packets that comply with the predetermined condition value via the first WAN port and forwards packets that do not comply with the predetermined condition value via a second WAN port. The packet forwarding device forwards some of the packets that do not comply with the predetermined condition value via the first WAN port in order to balance loads of the first and second WAN ports if the traffic value of the packets forwarded via the first WAN port is equal to or less than the predetermined threshold.Type: GrantFiled: April 19, 2010Date of Patent: August 21, 2012Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Kai-Yu Yang, Yao-Wen Chang
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Publication number: 20110182182Abstract: A packet forwarding device stores a predetermined threshold and a predetermined condition value of a first wide area network (WAN) port, and forwards packets that comply with the predetermined condition value via the first WAN port and forwards packets that do not comply with the predetermined condition value via a second WAN port. The packet forwarding device forwards some of the packets that do not comply with the predetermined condition value via the first WAN port in order to balance loads of the first and second WAN ports if the traffic value of the packets forwarded via the first WAN port is equal to or less than the predetermined threshold.Type: ApplicationFiled: April 19, 2010Publication date: July 28, 2011Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: KAI-YU YANG, YAO-WEN CHANG
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Patent number: D786185Type: GrantFiled: July 16, 2014Date of Patent: May 9, 2017Inventors: Xiao Jing Wang, Kai Yu Yang, Jian Ye Wang
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Patent number: D815019Type: GrantFiled: July 16, 2014Date of Patent: April 10, 2018Assignee: SAILUN JINYU GROUP CO., LTD.Inventors: Xiao Jing Wang, Kai Yu Yang, Jian Ye Wang
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Patent number: D842232Type: GrantFiled: July 16, 2014Date of Patent: March 5, 2019Assignee: SAILUNJINYU GROUP CO., LTD.Inventors: Xiao Jing Wang, Kai Yu Yang, Jian Ye Wang