Patents by Inventor Kai Yuan

Kai Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12194015
    Abstract: The present invention provides a composition, comprising ferrous amino acid chelate particles sintered from ferrous amino acid chelate, wherein the average particle size of the ferrous amino acid chelate particles ranges from 500 nm to 2600 nm, and the average molecular weight of the particles ranges from 1,500 Dalton to 600,000 Dalton. Besides, the present invention can be used for manufacturing a medicament for treating or ameliorating a pancreas-related disease, wherein the medicament comprises an effective amount of the composition and a pharmaceutically acceptable carrier.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 14, 2025
    Assignee: PROFEAT BIOTECHNOLOGY CO., LTD.
    Inventors: Tsun-Yuan Lin, Mu-Kuei Chen, Tsang-Tse Chen, Hsun-Jin Jan, Chai-Hui Fu, Kai-Ting Wang
  • Patent number: 12191198
    Abstract: Apparatus and methods to provide electronic devices comprising tungsten film stacks are provided. A tungsten liner formed by physical vapor deposition is filled with a tungsten film formed by chemical vapor deposition directly over the tungsten liner.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 7, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Feihu Wang, Joung Joo Lee, Xi Cen, Zhibo Yuan, Wei Lei, Kai Wu, Chunming Zhou, Zhebo Chen
  • Publication number: 20240428741
    Abstract: A display device includes a display panel including a plurality of gate lines and a plurality of data lines, the plurality of gate lines intersecting and being insulated with the plurality of data lines, the display panel further including a plurality of sub-pixels arranged in an array, and the plurality of gate lines and the plurality of data lines defining areas where the sub-pixels are located; a gate driver electrically connected to the plurality of gate lines in the display panel; and a source driver bound to the display panel and electrically connected to the plurality of data lines in the display panel, the source driver being configured to set data transmission start time for respective data lines so that effective charging time of respective sub-pixels formed by the plurality of data lines and a same gate line is same.
    Type: Application
    Filed: December 15, 2022
    Publication date: December 26, 2024
    Applicants: WUHAN BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE Technology Group Co., Ltd.
    Inventors: Jianmin Xiang, Lijun Xiao, Peng Jiang, Bing Li, Junmin Zhang, Meng Feng, Feng Jiang, Kai Cheng, Mengchao Shuai, Hangyu Chen, Yun Bai, Ziming Yang, Yuxi Xiang, Dongxu Yuan, Wei Fu
  • Patent number: 12166067
    Abstract: In some embodiments, the present disclosure relates to a method of forming a metal-insulator-metal (MIM) device. The method may be performed by depositing a bottom electrode layer over a substrate, depositing a dielectric layer over the bottom electrode layer, depositing a top electrode layer over the dielectric layer, and depositing a first titanium getter layer over the top electrode layer. The first titanium getter layer, the top electrode layer, and the dielectric layer are patterned to expose a peripheral portion of the bottom electrode layer. A passivation layer is deposited over the substrate, the first titanium getter layer, and the peripheral portion of the bottom electrode layer.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yan-Jie Liao
  • Patent number: 12166128
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Publication number: 20240404988
    Abstract: A bonded assembly may be formed by providing at least a first packaging substrate in a low-oxygen ambient; providing at least a first semiconductor package in the low-oxygen ambient; performing a first plasma package-treatment process on the first semiconductor package in the low-oxygen ambient by directing at least one first plasma jet to first solder material portions bonded to the first semiconductor package; and bringing the first solder material portions onto, or in proximity to, first substrate-side bonding structures located on the first packaging substrate while the at least one first plasma jet is directed to the first solder material portions. The first substrate-side bonding structures are treated with the first plasma jet. The first semiconductor package is bonded to the first packaging substrate while, or after, the first substrate-side bonding structures are treated with the first plasma jet.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Hui-Min Huang, Kai Jun Zhan, Ming-Da Cheng, Chih-Yuan Chiu, Amram Eitan
  • Publication number: 20240404989
    Abstract: A bonded assembly may be formed by providing a wafer comprising at least a first packaging substrate and a second packaging substrate in a low-oxygen ambient; performing a first plasma package-treatment process on the first semiconductor package in the low-oxygen ambient while performing a first substrate-treatment process on the first packaging substrate in a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa; and performing a second plasma package-treatment process on the second semiconductor package while performing a second substrate-treatment process on the second packaging substrate and while bonding the first semiconductor package to the first packaging substrate.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Hui-Min Huang, Kai Jun Zhan, Chih-Yuan Chiu, Ming-Da Cheng, Amram Eitan
  • Patent number: 12156778
    Abstract: A self-ligating bracket, a double-wing spacing adjustable bracket and a dental appliance are described. The self-ligating bracket includes a bracket base plate, a first elastic support, a bracket body, and a position-limited member. A first end of the first elastic support is connected to the bracket base plate. The bracket body has a hollow structure. A second end of the first elastic support is connected to a distal end of the bracket body. The distal end of the bracket body is provided with a distal-end gap. The distal end of the bracket body is expanded radially by the second end of the first elastic support. The position-limited member is movable in an axial direction of the bracket body, and the position-limited member is sleeved on an outside of the bracket body for overcoming elastic force provided by the first elastic support and making the bracket body contract in a radial direction.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: December 3, 2024
    Assignees: Peking University School of Stomatology, Center of Huanzhengduowei Education & Science and Technology, Beijing
    Inventors: Tian Min Xu, Kai Yuan Xu
  • Publication number: 20240395939
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Publication number: 20240394440
    Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Yuan TING, Hsin-Cheng Chen, Sandeep Kumar Goel, Mei Wong, Yun-Han Lee
  • Publication number: 20240387256
    Abstract: In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Yao-Min LIU, Ming-Yuan GAO, Ming-Chou CHIANG, Shu-Cheng CHIN, Huei-Wen HSIEH, Kai-Shiang KUO, Yen-Chun LIN, Cheng-Hui WENG, Chun-Chieh LIN, Hung-Wen SU
  • Patent number: 12144856
    Abstract: Miltefosine is utilized to enhance immune response to vaccination, for example an influenza and/or coronavirus vaccination. The inventive subject matter also provides compositions and methods for enhancing viral yield in cultured cells, by application of a cannabinoid receptor agonist (such as methanandamide) to such cells. Such enhanced viral yield can be used to enhance virus production for purposes of vaccine formulation and/or to improve sensitivity of cell-based virus assays.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 19, 2024
    Assignee: VERSITECH LIMITED
    Inventors: Kwok Yung Yuen, Kai Wang Kelvin To, Shuofeng Yuan, Fuk Woo Jasper Chan, Jinxia Zhang, Fan Ngai Hung, Johnson Yiu-Nam Lau
  • Publication number: 20240379659
    Abstract: A method includes: forming a fin protruding from a substrate; implanting an n-type dopant in the fin to form an n-type channel region; implanting a p-type dopant in the fin to form a p-type channel region adjacent the n-type channel region; forming a first gate structure over the n-type channel region and a second gate structure over the p-type channel region; forming a first epitaxial region in the fin adjacent a first side of the first gate structure; forming a second epitaxial region in the fin adjacent a second side of the first gate structure and adjacent a first side of the second gate structure; and forming a third epitaxial region in the fin adjacent a second side of the second gate structure.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Kai-Qiang Wen, Shih-Fen Huang, Shih-Chun Fu, Chi-Yuan Shih, Feng Yuan
  • Patent number: 12139379
    Abstract: An automatic loading system for vehicles includes an overhead platform, a transporting machine, and a cargo carrying mechanism. The overhead platform includes two rails. The transporting machine is disposed on the rails and configured to move on the rails along a first direction. The transporting machine includes a hoist mechanism and a fork assembly disposed on the hoist mechanism. The hoist mechanism is configured to drive the fork assembly to move along a second direction which is perpendicular to the first direction. The fork assembly includes forks disposed side by side and separately. Each fork includes at least a conveyer belt. The cargo carrying mechanism is configured to carry cargos and includes a conveyer belt platform. When the fork assembly is close to the cargo carrying mechanism, the conveyer belt and the conveyer belt platform are configured to transport the cargos to the forks from the conveyer belt platform.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: November 12, 2024
    Assignee: FORMOSA HEAVY INDUSTRIES CORPORATION
    Inventors: Jung-Hui Chen, Ting-Wang Yi, Yao-Yuan Shih, Kai-Siang Ho
  • Publication number: 20240373753
    Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Inventors: Alexander Kalnitsky, Chun-Ren Cheng, Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yan-Jie Liao
  • Publication number: 20240358665
    Abstract: The present disclosure relates to the field of hydrogel technology, and specifically relates to a small molecule melphalan hydrogel and a preparation method thereof. The small molecule melphalan hydrogel is made of melphalan drug or melphalan hydrochloride as raw materials, and it is formed at room temperature or physiological condition by means of making the melphalan drug in a hydrophilic solvent. The hydrophilic solvent includes any one of physiological saline, pure water, and phosphate buffered saline solution. The small molecule melphalan hydrogel provided by the present disclosure is an injectable hydrogel of 100% pure melphalan drug, the gel only contains small molecule melphalan drug, which solves the problems of containing a large amount of carrier materials and having a low drug loading rate in the field of hydrogel.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Applicant: Changzhi Medical College
    Inventors: Xiao Duan, Ting Li, Kai Yuan, Ningyue Lu, Yanbin He, Junbo Li
  • Patent number: 12128093
    Abstract: Methods of preventing and treating PKD and its complications using antibody activators that bind to the (Na++K+)-ATPase.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: October 29, 2024
    Inventor: Kai Yuan Xu
  • Publication number: 20240355578
    Abstract: Disclosed are non-transitory computer-readable media, systems, and computer-implemented methods that describe obtaining hot spot (HS) location information with respect to a printed pattern; obtaining LFP search criteria for searching the printed pattern to determine a local focus point (LFP) for an imaging device; selecting a HS area in the printed pattern that contains a HS; and determining the LFP proximate to the HS area based on the LFP search criteria, the LFP not containing the HS.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Te-Sheng WANG, Szu-Po WANG, Kai-Yuan CHI
  • Publication number: 20240355106
    Abstract: A method for training a segmentation model is provided. The method includes using first training images to train a segmentation model. The method includes using second training images to train an image generator. The method includes inputting real images into the segmentation model to generate predicted annotation images. The method includes inputting the predicted annotation images into the image generator to generate fake images. The method includes updating the segmentation model and the image generator according to a loss caused by differences between the real images and the fake images.
    Type: Application
    Filed: November 27, 2023
    Publication date: October 24, 2024
    Inventors: Chia-Yuan CHANG, Kai-Ju CHENG, Shao-Ang CHEN, Kuan-Chung CHEN
  • Publication number: 20240345079
    Abstract: The present invention provides a test device. The device includes a testing element and a house configured to accommodate the testing element, where the house is formed by folding a paper-made card, and the testing element is located in the housing. The housing is allowed to be in different change states to test or assay an analyte in a sample.
    Type: Application
    Filed: May 9, 2024
    Publication date: October 17, 2024
    Inventors: Guoliang YUAN, Jianqiu FANG, Siyu LEI, Kai FANG