Abstract: Embodiments provide a method for manufacturing a device. The method comprises providing a first carrier having attached thereto a plurality of chips by means of an adhesive layer of the first carrier, a first surface of the plurality of chips being attached to the first carrier. Further, the method comprises selectively attaching a second surface of a subset of the plurality of chips to a conveyor carrier by means of a structured adhesive layer of the conveyor layer. Further, the method comprises selectively releasing the subset of the plurality of chips from the first carrier by means of debonding corresponding sections of the adhesive layer of the first carrier. Further, the method comprises attaching the first surface of the subset of the plurality of chips to a substrate of the device.

Abstract: Disclosed is a system for and a method of manufacturing of an optical system, including a first optical component, comprising a first waveguide and a carrier substrate, wherein the first optical component is arranged on the carrier substrate. The first optical component comprises a first markup set having a defined position/orientation with respect to the first waveguide, the carrier substrate has a second markup set detectable based on a relative position/orientation of the first and second markup sets when a desired orientation of the first waveguide relative to the carrier substrate is achieved in a reference plane extending parallel to a surface of the carrier substrate.

Abstract: A method for manufacturing a plurality of, in particular hermetically, sealed functional elements, comprising the following steps: providing a first wafer comprising the plurality of functional elements, providing a second wafer, applying a sealing material in the form of a plurality of frame structures on a first surface of the second wafer, placing the second wafer on the first wafer or vice versa, joining the first wafer with the second wafer.

Abstract: The invention relates to a carrier arrangement (100; 500; 600; 700; 800; 900; 1000), and a method for producing a carrier arrangement. The method comprises: producing a layer (130; 530; 630; 730; 830; 930; 1030) on a surface (120; 520; 620; 720; 820; 920; 1020) of a carrier (110; 510; 610; 710; 810; 910; 1010), the layer comprising a first region (131; 531; 631; 731; 831; 931; 1031) and a second region (132; 532; 632; 732; 832; 932; 1032) connected to the first region, the first region covering a first surface region (121; 521; 621; 721; 821; 921; 1021) of the carrier and the second region covering a second surface region (122; 722; 922) of the carrier, detaching the second region of the layer from the carrier, the first region of the layer remaining on the first surface region of the carrier and not being separated from the second region, the layer being flexible in the detached second region.

Abstract: A module unit includes a carrier substrate and an antenna substrate. The carrier substrate at least includes an embedded chip and a redistribution layer arranged on the first main surface. The antenna substrate including a base material includes an antenna structure arranged on the side of the first main surface, and a cavity introduced on the side of the second main surface, the cavity being aligned with the antenna structure at least in areas. The antenna substrate is connected with the second main surface to the first main surface of the carrier substrate, so that the antenna substrate and the carrier substrate form a layer stack.

Abstract: Disclosed is a system for and a method of manufacturing of an optical system, including a first optical component, comprising a first waveguide and a carrier substrate, wherein the first optical component is arranged on the carrier substrate. The first optical component comprises a first markup set having a defined position/orientation with respect to the first waveguide, the carrier substrate has a second markup set detectable based on a relative position/orientation of the first and second markup sets when a desired orientation of the first waveguide relative to the carrier substrate is achieved in a reference plane extending parallel to a surface of the carrier substrate.

Abstract: A method for manufacturing a semiconductor component including: providing a flat carrier with an upper side and a lower side, the carrier including a continuous opening that runs between the upper side and the lower side; providing a semiconductor arrangement that includes a semiconductor chip that includes electrically and/or optically active regions on a lower side; arranging the semiconductor arrangement in the opening such that a lower side of the semiconductor arrangement and the lower side of the carrier run in a common plane; casting the semiconductor arrangement with a potting compound, such that the semiconductor arrangement is materially connected to the carrier; and thinning out the semiconductor system by way of grinding from above, such that an upper side of the carrier and an upper side of the semiconductor arrangement run in a common plane.

Abstract: A module unit includes a carrier substrate and an antenna substrate. The carrier substrate at least includes an embedded chip and a redistribution layer arranged on the first main surface. The antenna substrate including a base material includes an antenna structure arranged on the side of the first main surface, and a cavity introduced on the side of the second main surface, the cavity being aligned with the antenna structure at least in areas. The antenna substrate is connected with the second main surface to the first main surface of the carrier substrate, so that the antenna substrate and the carrier substrate form a layer stack.

Abstract: A method for manufacturing a semiconductor component including: providing a flat carrier with an upper side and a lower side, the carrier including a continuous opening that runs between the upper side and the lower side; providing a semiconductor arrangement that includes a semiconductor chip that includes electrically and/or optically active regions on a lower side; arranging the semiconductor arrangement in the opening such that a lower side of the semiconductor arrangement and the lower side of the carrier run in a common plane; casting the semiconductor arrangement with a potting compound, such that the semiconductor arrangement is materially connected to the carrier; and thinning out the semiconductor system by way of grinding from above, such that an upper side of the carrier and an upper side of the semiconductor arrangement run in a common plane.

Abstract: The present invention relates to a bonding method for connecting a first wafer and a second wafer, wherein firstly a first adhesive layer is deposited onto a surface of the first wafer. Furthermore, a second adhesive layer is deposited onto the first adhesive layer, and the two adhesive layers are structured by way of selective removal of both adhesive layers in at least one predefined region of the first wafer, Moreover, the first wafer is connected to the second wafer by way of pressing a surface of the second wafer onto the second adhesive layer, wherein the second adhesive layer is more flowable that the first adhesive layer on connecting the first wafer to the second wafer.

Abstract: A method for manufacturing metal structures for the electrical connection of components comprises the following steps: depositing an auxiliary layer on a substrate; structuring the auxiliary layer in a manner such that the substrate is exposed at least one environment which is envisaged for the metal structures; depositing a galvanic starting layer on the structured auxiliary layer; depositing a lithography layer on the galvanic starting layer and structuring the lithography layer in a manner such that the galvanic starting layer is exposed at least one location envisaged for the metal structure; galvanically depositing the at least one metal structure at the at least one exposed location; removing the structured auxiliary layer. An electronic component is also described.

Abstract: A method for arranging electronic components that includes a plurality of electronic components pasted onto a first front face of a carrier having a bonding layer. The front face and/or the electronic components being provided with a plurality of bonding points and the diameter of and distance between the bonding points are selected such that each of the plurality of electronic components is attached by at least three bonding points to the carrier having the bonding layer. The method also includes arranging at least one portion of the plurality of the components on a switching element carrier and connecting the components to the carrier. The method also includes detaching a component from the carrier having a bonding layer, using a solvent or a mechanical force that separates the carrier having a bonding layer and the switching element carrier from one another.

Abstract: The present invention relates to a bonding method for connecting a first wafer and a second wafer, wherein firstly a first adhesive layer is deposited onto a surface of the first wafer. Furthermore, a second adhesive layer is deposited onto the first adhesive layer, and the two adhesive layers are structured by way of selective removal of both adhesive layers in at least one predefined region of the first wafer, Moreover, the first wafer is connected to the second wafer by way of pressing a surface of the second wafer onto the second adhesive layer, wherein the second adhesive layer is more flowable that the first adhesive layer on connecting the first wafer to the second wafer.

Abstract: The application describes a method for manufacturing metal structures for the electrical connection of components. The method comprises the following steps: depositing an auxiliary layer on a substrate; structuring the auxiliary layer in a manner such that the substrate is exposed at least one environment which is envisaged for the metal structures; depositing a galvanic starting layer on the structured auxiliary layer; depositing a lithography layer on the galvanic starting layer and structuring the lithography layer in a manner such that the galvanic starting layer is exposed at least one location envisaged for the metal structure; galvanically depositing the at least one metal structure at the at least one exposed location; removing the structured auxiliary layer. An electronic component is also described.

Abstract: A method for arranging electronic components, can comprise the following steps: a) at least one, preferably a plurality of electronic components are pasted onto a first front face of a carrier having a bonding layer, i.e.

Abstract: The present invention relates to a functional unit, containing at least one active or passive electronic component, the functional unit being surrounded by at least one flexible dielectric layer and, on the outer side of the functional unit, contacts are provided for contacting the electrical components for further mounting.