Patents by Inventor Kaichi Zhang
Kaichi Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9208083Abstract: A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a first sector size and a second sector size. The interleaver selectively interleaves information stored in a first memory and/or a second memory in response to a sector select signal. The storage device selectively provides the first masking seed and/or a second masking seed to the interleaver in response to the sector select signal. Corresponding methods are also disclosed.Type: GrantFiled: January 31, 2014Date of Patent: December 8, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Yang Han, Zongwang Li, Shaohua Yang, Kaichi Zhang
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Publication number: 20150154114Abstract: A memory interleaving apparatus includes first and second interleavers. The first interleaver selectively interleaves information stored in a first memory in response to a sector select signal. The second interleaver selectively interleaves information stored in a second memory in response the sector select signal. The first interleaver is coupled with the second interleaver. A memory interleaving system includes an interleaver and a storage device. The interleaver is associated with a first sector size and a second sector size. The interleaver selectively interleaves information stored in a first memory and/or a second memory in response to a sector select signal. The storage device selectively provides the first masking seed and/or a second masking seed to the interleaver in response to the sector select signal. Corresponding methods are also disclosed.Type: ApplicationFiled: January 31, 2014Publication date: June 4, 2015Applicant: LSI CorporationInventors: Yang Han, Zongwang Li, Shaohua Yang, Kaichi Zhang
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Patent number: 9037952Abstract: A hard decision memory interacts with a multi-layered low-density parity-check decoder by sending multiple L values and E values to a multi-layered low-density parity-check decoder (LDPC), and the L value E value hard decision memory (LE hard decision memory) receives one or more hard decisions. The LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements. The use of the LE hard decision memory results improved multi-level LDPC decoding of an LDPC encoded message.Type: GrantFiled: February 6, 2013Date of Patent: May 19, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Zongwang Li, Yang Han, Kaichi Zhang, Chung-Li Wang
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Patent number: 8850276Abstract: Various embodiments of the present invention provide systems and methods for data processing. Such data processing includes data shuffling.Type: GrantFiled: September 22, 2011Date of Patent: September 30, 2014Assignee: LSI CorporationInventors: Changyou Xu, Zongwang Li, Sancar K. Olcay, Yang Han, Kaichi Zhang
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Publication number: 20140223259Abstract: A LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements.Type: ApplicationFiled: February 6, 2013Publication date: August 7, 2014Applicant: LSI CORPORATIONInventors: Zongwang Li, Yang Han, Kaichi Zhang, Chung-Li Wang
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Publication number: 20130080844Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes: receiving a data input having at least a first local chunk and a second local chunk, the data input also being defined as having at least a first global chunk and a second global chunk; rearranging an order of the first local chunk and the second local chunk to yield a locally interleaved data set; storing the locally interleaved data set to a first memory, such that the first global chunk is stored to a first memory space, and the second global chunk is stored to a second memory space; accessing the locally interleaved data set from the first memory; and storing the locally interleaved data set to a second memory. The first global chunk is stored to a third memory space defined at least in part based on the first memory space, and the second global chunk is stored to a fourth memory space defined at least in part based on the second memory space.Type: ApplicationFiled: September 22, 2011Publication date: March 28, 2013Inventors: Changyou Xu, Zongwang Li, Sancar K. Olcay, Yang Han, Kaichi Zhang
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Patent number: 8223827Abstract: A method and apparatus are provided for determining a plurality of filter tap weights or biases (or both) for a noise predictive filter used to generate one or more signal dependent branch metrics. A filter tap weight or filter bias (or both) are adaptively accumulated for each possible data condition. The data conditions may comprise, for example, each possible data pattern for a given data dependency length. The appropriate accumulated filter tap weight or bias to update can be selected based on a data condition associated with the current received data. The filter tap weights associated with a delay 0 tap can be adapted for each filter condition except for a single normalizing condition, whose corresponding delay 0 tap remains fixed.Type: GrantFiled: May 5, 2004Date of Patent: July 17, 2012Assignee: Agere Systems Inc.Inventors: Jonathan James Ashley, Keenan Terrell O'Brien, Richard Rauschmayer, Sumeet Sanghvi, Anne Q. Ye, Kaichi Zhang
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Patent number: 7561649Abstract: A method and apparatus are disclosed for detecting a synchronization mark in a received signal. The received signal is processed to compensate for a DC bias in the received signal, such as subtracting an average of a block of received samples from each sample in the block. A distance metric, such as a sum of square differences, is computed between the DC compensated received signal and an ideal version of the received signal expected when reading the synchronization mark. The synchronization mark is detected if the distance metric satisfies predefined criteria. The ideal version of the received signal can optionally be processed to compensate for a DC bias in the synchronization mark. A search for the synchronization mark search can be limited to time cycles that match a known phase.Type: GrantFiled: April 30, 2004Date of Patent: July 14, 2009Assignee: Agere Systems Inc.Inventors: Jonathan James Ashley, Ching-Fu Wu, Kaichi Zhang
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Patent number: 7137056Abstract: The present invention relates to a coding system characterized by various combinations of the following properties: 1) Even parity at the output of d of the precoder; 2) A coding rate of 32/34; 3) At least 9 ones per codeword; 4) No more than 13 consecutive zeros in the stream of encoded data (G=13); 5) No more than 13 consecutive zeros in any run of every-other-bit in the stream of codewords (I=13); 6) For closed error events in y or y? having squared-distance?(1 to 1.5)×dmfb2 in the detector, the decoder produces at most 4 corresponding erroneous data bytes; 7) Decoding of a 34 bit codeword may begin when 19 of its bits have been received; 8) If the Viterbi detector 108 outputs Non-Return to Zero (NRZ) symbols, then its output is filtered by (1?D^2) before being decoded, but if the Viterbi detector outputs NRZ Inverter (NRZI) symbols, then its output is decoded directly; and 9) The even parity is on NRZ symbols.Type: GrantFiled: September 25, 2002Date of Patent: November 14, 2006Assignee: Infineon Technologies North America Corp.Inventors: Jonathan Ashley, William G. Bliss, Razmik Karabed, Kaichi Zhang
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Publication number: 20050249273Abstract: A method and apparatus are provided for determining a plurality of filter tap weights or biases (or both) for a noise predictive filter used to generate one or more signal dependent branch metrics. A filter tap weight or filter bias (or both) are adaptively accumulated for each possible data condition. The data conditions may comprise, for example, each possible data pattern for a given data dependency length. The appropriate accumulated filter tap weight or bias to update can be selected based on a data condition associated with the current received data. The filter tap weights associated with a delay 0 tap can be adapted for each filter condition except for a single normalizing condition, whose corresponding delay 0 tap remains fixed.Type: ApplicationFiled: May 5, 2004Publication date: November 10, 2005Inventors: Jonathan Ashley, Keenan O'Brien, Richard Rauschmayer, Sumeet Sanghvi, Anne Ye, Kaichi Zhang
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Publication number: 20050243959Abstract: A method and apparatus are disclosed for detecting a synchronization mark in a received signal. The received signal is processed to compensate for a DC bias in the received signal, such as subtracting an average of a block of received samples from each sample in the block. A distance metric, such as a sum of square differences, is computed between the DC compensated received signal and an ideal version of the received signal expected when reading the synchronization mark. The synchronization mark is detected if the distance metric satisfies predefined criteria. The ideal version of the received signal can optionally be processed to compensate for a DC bias in the synchronization mark. A search for the synchronization mark search can be limited to time cycles that match a known phase.Type: ApplicationFiled: April 30, 2004Publication date: November 3, 2005Inventors: Jonathan Ashley, Ching-Fu Wu, Kaichi Zhang
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Patent number: 6809894Abstract: A method and apparatus for handling end of data processing in a data storage device. The method includes receiving a plurality of user data bits at a write channel. The method further includes appending primary padding bits to user data bits if the plurality of user data bits is less than a multiple of an input block length of an encoder in the write channel and encoding the plurality of user data bits and any primary padding bits into a plurality of encoded data bytes. Additionally, the method includes appending an end of data marker to an end of the plurality of encoded data bytes, wherein the end of data marker has a length of no more than one byte, and writing the plurality of encoded data bytes and the end of data marker to the data store.Type: GrantFiled: June 29, 2001Date of Patent: October 26, 2004Assignee: Infineon Technologies AGInventors: William G. Bliss, Razmik Karabed, James W. Rae, Heiner Stockmanns, Kaichi Zhang
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Publication number: 20040059993Abstract: The present invention relates to a coding system characterized by various combinations of the following properties: 1) Even parity at the output of d of the precoder; 2) A coding rate of 32/34; 3) At least 9 ones per codeword; 4) No more than 13 consecutive zeros in the stream of encoded data (G=13); 5) No more than 13 consecutive zeros in any run of every-other-bit in the stream of codewords (I=13); 6) For closed error events in y or y′ having squared-distance≦(1 to 1.5)×dmfb2 in the detector, the decoder produces at most 4 corresponding erroneous data bytes; 7) Decoding of a 34 bit codeword may begin when 19 of its bits have been received; 8) If the Viterbi detector 108 outputs Non-Return to Zero (NRZ) symbols, then its output is filtered by (1⊕D{circumflex over ( )}2) before being decoded, but if the Viterbi detector outputs NRZ Inverter (NRZI) symbols, then its output is decoded directly; and 9) The even parity is on NRZ symbols.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Applicant: Infineon TechnologiesInventors: Jonathan Ashley, William G. Bliss, Razmik Karabed, Kaichi Zhang
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Publication number: 20030002188Abstract: A method and apparatus for handling end of data processing in a data storage device. The method includes receiving a plurality of user data bits at a write channel. The method further includes appending primary padding bits to user data bits if the plurality of user data bits is less than a multiple of an input block length of an encoder in the write channel and encoding the plurality of user data bits and any primary padding bits into a plurality of encoded data bytes. Additionally, the method includes appending an end of data marker to an end of the plurality of encoded data bytes, wherein the end of data marker has a length of no more than one byte, and writing the plurality of encoded data bytes and the end of data marker to the data store.Type: ApplicationFiled: June 29, 2001Publication date: January 2, 2003Inventors: William G. Bliss, Razmik Karabed, James W. Rae, Heiner Stockmanns, Kaichi Zhang