Patents by Inventor Kai-Chun Lin
Kai-Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996433Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a dielectric layer having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall of the dielectric layer. A first conductive layer contacts a bottom surface of the dielectric layer. The sidewall of the dielectric layer is directly over the first conductive layer. A second conductive layer contacts the first conductive layer and the dielectric layer. The second conductive layer vertically extends from the first conductive layer to above the dielectric layer. A third conductive layer contacts the second conductive layer. The third conductive layer is laterally separated from a sidewall of the second conductive layer that faces the third conductive layer by a non-zero distance.Type: GrantFiled: April 26, 2022Date of Patent: May 28, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Chun Hsu, Ching-Chun Wang, Dun-Nian Yaung, Jeng-Shyan Lin, Shyh-Fann Ting
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Patent number: 11990100Abstract: An e-paper identification card system including an e-paper identification card and a data updating apparatus is provided. The e-paper identification card is configured to display first image information. The data updating apparatus is electrically connected to the e-paper identification card. The data updating apparatus is configured to update the e-paper identification card according to the first image information to drive the e-paper identification card to display second image information. In addition, an e-paper identification card is also provided.Type: GrantFiled: January 12, 2023Date of Patent: May 21, 2024Assignee: E Ink Holdings Inc.Inventors: Chih-Chun Chen, Huei-Chuan Lee, Cheng-Hsien Lin, Shuo-En Lee, Kai-Yi Cho
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Publication number: 20240115616Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.Type: ApplicationFiled: October 4, 2023Publication date: April 11, 2024Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
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Publication number: 20240121373Abstract: Disclosed are an image display method and a 3d display system. The method is adapted to the 3d display system including a 3d display device and includes the following steps. A first image and a second image are obtained by splitting an input image according to a 3d image format. Whether the input image is a 3D format image complying with the 3D image format is determined through a stereo matching processing performed on the first image and the second image. An image interweaving process is enabled to be performed on the input image to generate an interweaving image in response to determining that the input image is the 3D format image complying with the 3D image format, and the interweaving image is displayed via the 3D display device.Type: ApplicationFiled: May 10, 2023Publication date: April 11, 2024Applicant: Acer IncorporatedInventors: Kai-Hsiang Lin, Hung-Chun Chou, Wen-Cheng Hsu, Shih-Hao Lin, Chih-Haw Tan
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Publication number: 20240107414Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Yu-Chieh HUANG, Kuhn-Chang LIN, Jen-Chun CHANG, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yeong Leong CHOO, Chun-Hsiang CHIU, Chihhung HSIEH, Kai-Chun CHENG, Chung Wei LIN
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Patent number: 11923251Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.Type: GrantFiled: May 7, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
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Patent number: 11800122Abstract: A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.Type: GrantFiled: February 23, 2022Date of Patent: October 24, 2023Assignee: MEDIATEK INC.Inventors: Chih-Wen Yang, Chi-Hung Chen, Kai-Chun Lin, Chien-Wei Lin, Meng-Jye Hu
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Publication number: 20230064790Abstract: A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.Type: ApplicationFiled: July 29, 2022Publication date: March 2, 2023Applicant: MEDIATEK INC.Inventors: Kai-Chun Lin, Chi-Hung Chen, Meng-Jye Hu, Hsiao-En Chen, Chih-Wen Yang, Chien-Wei Lin
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Publication number: 20230054524Abstract: A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.Type: ApplicationFiled: February 23, 2022Publication date: February 23, 2023Applicant: MEDIATEK INC.Inventors: Chih-Wen Yang, Chi-Hung Chen, Kai-Chun Lin, Chien-Wei Lin, Meng-Jye Hu
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Publication number: 20230021722Abstract: A motion vector refinement apparatus includes a storage device, a reference block fetch circuit, and a processing circuit. The reference block fetch circuit fetches a forward reference block and a backward reference block according to at least specified motion vectors (MVs) of a current block, and stores the forward reference block and the backward reference block into the storage device. The processing circuit derives a first reference block from the forward reference block and a second reference block from the backward reference block, calculates at least one accumulated pixel difference (APD) value for at least one block pair each having a first block found in the first reference block and a second block found in the second reference block, and determines an offset setting for motion vector refinement of the specified MVs according to the at least one APD value.Type: ApplicationFiled: January 27, 2022Publication date: January 26, 2023Applicant: MEDIATEK INC.Inventors: Kai-Chun Lin, Sheng-Jen Wang, Chi-Hung Chen
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Patent number: 10939102Abstract: A post processing apparatus includes a super-resolution (SR) filtering circuit and a loop restoration (LR) filtering circuit. The SR filtering circuit applies SR filtering to a processing result of a preceding circuit. The LR filtering circuit applies LR filtering to a processing result of the SR filtering circuit. Before the SR filtering circuit finishes SR filtering of all pixels of a frame that are generated by the preceding circuit, the LR filtering circuit starts LR filtering of pixels that are derived from applying SR filtering to pixels included in the frame.Type: GrantFiled: October 28, 2019Date of Patent: March 2, 2021Assignee: MEDIATEK INC.Inventors: Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Chi-Hung Chen, Kai-Chun Lin, Chih-Wen Yang, Hsuan-Wen Peng
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Patent number: 10714535Abstract: A method includes forming an insulator over a substrate. The insulator includes a first electrode, a second electrode, and a resistive element between the first electrode and the second electrode. The insulator is transformed into a resistor by applying a voltage to the insulator. The resistor is electrically connected to a transistor after transforming the insulator into the resistor.Type: GrantFiled: December 21, 2018Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ku-Feng Lin, Hung-Chang Yu, Kai-Chun Lin, Yu-Der Chih
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Publication number: 20200145658Abstract: A post processing apparatus includes a super-resolution (SR) filtering circuit and a loop restoration (LR) filtering circuit. The SR filtering circuit applies SR filtering to a processing result of a preceding circuit. The LR filtering circuit applies LR filtering to a processing result of the SR filtering circuit. Before the SR filtering circuit finishes SR filtering of all pixels of a frame that are generated by the preceding circuit, the LR filtering circuit starts LR filtering of pixels that are derived from applying SR filtering to pixels included in the frame.Type: ApplicationFiled: October 28, 2019Publication date: May 7, 2020Inventors: Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Chi-Hung Chen, Kai-Chun Lin, Chih-Wen Yang, Hsuan-Wen Peng
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Patent number: 10372948Abstract: A memory device is provided which comprises a memory array, a first scrambling circuit and a second scrambling circuit. The first scrambling circuit is configured to provide first scrambled data with a first scrambling pattern in response to input data. The second scrambling circuit is configured to provide second scrambled data with a second scrambling pattern in response to the first scrambled data.Type: GrantFiled: December 15, 2015Date of Patent: August 6, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kai-Chun Lin, Ku-Feng Lin, Hung-Chang Yu, Yu-Der Chih
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Patent number: 10281942Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: GrantFiled: February 26, 2018Date of Patent: May 7, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
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Publication number: 20190123107Abstract: A method includes forming an insulator over a substrate. The insulator includes a first electrode, a second electrode, and a resistive element between the first electrode and the second electrode. The insulator is transformed into a resistor by applying a voltage to the insulator. The resistor is electrically connected to a transistor after transforming the insulator into the resistor.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ku-Feng LIN, Hung-Chang YU, Kai-Chun LIN, Yu-Der CHIH
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Patent number: 10163980Abstract: A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.Type: GrantFiled: May 26, 2016Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ku-Feng Lin, Hung-Chang Yu, Kai-Chun Lin, Yu-Der Chih
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Publication number: 20180188756Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: ApplicationFiled: February 26, 2018Publication date: July 5, 2018Inventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih
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Publication number: 20180184469Abstract: A method for wirelessly connecting to an internet, applied for establishing a wireless connection between a mobile device and a plurality of wireless networking devices, the method including: the mobile device searching for the plurality of wireless networking devices via a wireless communication; the mobile device wirelessly connecting with a main controlling device which is one of the plurality of wireless networking devices; the mobile device providing a connection information to the main controlling device for connecting to a base station; and the main controlling device broadcasting the connection information to the other wireless networking devices of the plurality of wireless networking devices; and the main controlling device and the other wireless networking devices of the plurality of wireless networking devices connecting to the base station according to the connection information.Type: ApplicationFiled: December 28, 2017Publication date: June 28, 2018Inventors: CHIN-MIN HUANG, MENG-SHIN LEE, KAI-CHUN LIN, CHI-SHENG WANG
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Patent number: 9910451Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.Type: GrantFiled: February 17, 2014Date of Patent: March 6, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yuan-Long Siao, Ku-Feng Lin, Kai-Chun Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih