Patents by Inventor Kaihan Ashtiani
Kaihan Ashtiani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10895539Abstract: A system includes a camera mounted external to and adjacent to a window of a processing chamber configured to process semiconductor substrates. The window allows the camera to view a component in the processing chamber. The camera is configured to generate a video signal indicative of a status of the component during a process being performed in the processing chamber. The system further includes a controller coupled to the processing chamber. The controller is configured to control the camera, process the video signal from the camera, determine the status of the component based on the processing of the video signal, and determine whether to terminate the process based on the status of the component.Type: GrantFiled: September 24, 2018Date of Patent: January 19, 2021Assignee: LAM RESEARCH CORPORATIONInventors: Kapil Sawlani, Gary B. Lind, Michal Danek, Ronald Powell, Michael Rumer, Kaihan Ashtiani
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Publication number: 20190120775Abstract: A system includes a camera mounted external to and adjacent to a window of a processing chamber configured to process semiconductor substrates. The window allows the camera to view a component in the processing chamber. The camera is configured to generate a video signal indicative of a status of the component during a process being performed in the processing chamber. The system further includes a controller coupled to the processing chamber. The controller is configured to control the camera, process the video signal from the camera, determine the status of the component based on the processing of the video signal, and determine whether to terminate the process based on the status of the component.Type: ApplicationFiled: September 24, 2018Publication date: April 25, 2019Inventors: Kapil Sawlani, Gary B. Lind, Michal Danek, Ronald Powell, Michael Rumer, Kaihan Ashtiani
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Patent number: 10262943Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: GrantFiled: January 23, 2018Date of Patent: April 16, 2019Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Publication number: 20180151503Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: ApplicationFiled: January 23, 2018Publication date: May 31, 2018Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Patent number: 9875968Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: GrantFiled: February 24, 2017Date of Patent: January 23, 2018Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Publication number: 20170162512Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: ApplicationFiled: February 24, 2017Publication date: June 8, 2017Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Patent number: 9583386Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: GrantFiled: October 2, 2015Date of Patent: February 28, 2017Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Patent number: 9406544Abstract: A method for filling a trench in a substrate includes partially filling the trench with a first silicon dioxide layer. An amorphous silicon layer is deposited on the silicon dioxide layer. The trench is filled with a second silicon dioxide layer. An oxidation treatment is performed on the substrate to oxidize the amorphous silicon layer.Type: GrantFiled: June 12, 2015Date of Patent: August 2, 2016Assignee: LAM RESEARCH CORPORATIONInventors: Wei Tang, Jason Daejin Park, Bart Van Schravendijk, Kaihan Ashtiani
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Publication number: 20160118296Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: ApplicationFiled: October 2, 2015Publication date: April 28, 2016Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Patent number: 9299559Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.Type: GrantFiled: August 22, 2014Date of Patent: March 29, 2016Assignee: Novellus Systems, Inc.Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
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Publication number: 20160013020Abstract: Systems and methods for producing energetic neutrals include a remote plasma generator configured to generate plasma in a plasma region. An ion extractor is configured to extract high energy ions from the plasma. A substrate support is arranged in a processing chamber and is configured to support a substrate. A neutral extractor and gas dispersion device is arranged between the plasma region and the substrate support. The neutral extractor and gas dispersion device is configured to extract energetic neutrals from the high energy ions, to supply the energetic neutrals to the substrate and to disperse precursor gas into the processing chamber.Type: ApplicationFiled: June 16, 2015Publication date: January 14, 2016Inventors: Kaihan Ashtiani, Canfeng Lai, Liang Meng
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Publication number: 20150118863Abstract: Provided herein are methods and apparatus for forming flowable dielectric films having low porosity. In some embodiments, the methods involve plasma post-treatments of flowable dielectric films. The treatments can involve exposing a flowable film to a plasma while the film is still in a flowable, reactive state but after deposition of new material has ceased.Type: ApplicationFiled: October 21, 2014Publication date: April 30, 2015Inventors: Megha Rathod, Deenesh Padhi, Nerissa Draeger, Bart J. van Schravendijk, Kaihan Ashtiani
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Publication number: 20150044882Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.Type: ApplicationFiled: August 22, 2014Publication date: February 12, 2015Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
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Publication number: 20140302689Abstract: Methods for depositing flowable dielectric films are provided. In some embodiments, the methods involve introducing a silicon-containing precursor to a deposition chamber wherein the precursor is characterized by having a partial pressure:vapor pressure ratio between 0.01 and 1. In some embodiments, the methods involve depositing a high density plasma dielectric film on a flowable dielectric film. The high density plasma dielectric film may fill a gap on a substrate. Also provided are apparatuses for performing the methods.Type: ApplicationFiled: April 9, 2014Publication date: October 9, 2014Applicant: Novellus Systems, Inc.Inventors: Kaihan Ashtiani, Michael Wood, John Drewery, Naohiro Shoda, Bart van Schravendijk, Lakshminarayana Nittala, Nerissa Draeger
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Patent number: 8846536Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.Type: GrantFiled: June 11, 2012Date of Patent: September 30, 2014Assignee: Novellus Systems, Inc.Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
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Patent number: 8728958Abstract: Novel gap fill schemes involving depositing both flowable oxide films and high density plasma chemical vapor deposition oxide (HDP oxide) films are provided. According to various embodiments, the flowable oxide films may be used as a sacrificial layer and/or as a material for bottom up gap fill. In certain embodiments, the top surface of the filled gap is an HDP oxide film. The resulting filled gap may be filled only with HDP oxide film or a combination of HDP oxide and flowable oxide films. The methods provide improved top hat reduction and avoid clipping of the structures defining the gaps.Type: GrantFiled: December 9, 2010Date of Patent: May 20, 2014Assignee: Novellus Systems, Inc.Inventors: Kaihan Ashtiani, Michael Wood, John Drewery, Naohiro Shoda, Bart van Schravendijk, Lakshminarayana Nittala, Nerissa Draeger
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Publication number: 20130230987Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.Type: ApplicationFiled: June 11, 2012Publication date: September 5, 2013Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
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Patent number: 8409985Abstract: The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 ??-cm for a 500 Angstrom film may be obtained.Type: GrantFiled: April 27, 2011Date of Patent: April 2, 2013Assignee: Novellus Systems, Inc.Inventors: Lana Hiului Chan, Kaihan Ashtiani, Joshua Collins
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Patent number: 8409987Abstract: Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the deposited nucleation layer prior to depositing the bulk tungsten fill. The treatment operation lowers resistivity of the deposited tungsten film. In certain embodiments, the depositing the nucleation layer involves a boron-based chemistry in the absence of hydrogen. Also in certain embodiments, the treatment operations involve exposing the nucleation layer to alternating cycles of a reducing agent and a tungsten-containing precursor. The methods are useful for depositing films in high aspect ratio and/or narrow features. The films exhibit low resistivity at narrow line widths and excellent step coverage.Type: GrantFiled: September 23, 2011Date of Patent: April 2, 2013Assignee: Novellus Systems, Inc.Inventors: Anand Chandrashekar, Mirko Glass, Raashina Humayun, Michal Danek, Kaihan Ashtiani, Feng Chen, Lana Hiului Chan, Anil Mane
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Patent number: 8367546Abstract: Novel low-resistivity tungsten film stack schemes and methods for depositing them are provided. The film stacks include a mixed tungsten/tungsten-containing compound (e.g., WC) layer as a base for deposition of tungsten nucleation and/or bulk layers. According to various embodiments, these tungsten rich layers may be used as barrier and/or adhesion layers in tungsten contact metallization and bitlines. Deposition of the tungsten-rich layers involves exposing the substrate to a halogen-free organometallic tungsten precursor. The mixed tungsten/tungsten carbide layer is a thin, low resistivity film with excellent adhesion and a good base for subsequent tungsten plug or line formation.Type: GrantFiled: October 18, 2011Date of Patent: February 5, 2013Assignee: Novellus Systems, Inc.Inventors: Raashina Humayun, Kaihan Ashtiani, Karl B. Levy