Abstract: Provided are transaminase mutants and uses thereof. The transaminase mutant is obtained by one or more amino acid mutations occurring in SEQ ID NO: 2 or is a mutant with a conserved amino acid mutation obtained by taking the sequence SEQ ID NO: 1 of a wild-type CvTA transaminase as a reference. Compared with wild-type transaminases, the catalytic activity of the mutant is improved to different degrees, so that the production efficiency of chiral amine compound synthesis may be improved.

Abstract: Disclosed are a memory array, a memory, a preparing method and a writing method. Some embodiments relate to a memory array for a magnetoresistive random access memory and a manufacturing method thereof. The memory array includes: a plurality of memory cells arranged in an array and a conductor layer; each of the memory cells includes: a write transistor, a first end of which is coupled to top electrode wiring; a magnetic tunnel junction MTJ, one end of which close to a reference layer is coupled to a second end of the write transistor; a side surface of the conductor layer is coupled to end faces of one end of all of the magnetic tunnel junctions MTJs close to a free layer.

Abstract: The present disclosure provides a multi-bit memory cell, an analog-to-digital converter, a device and a method. The multi-bit memory cell comprises: a spin-orbit coupling layer and a plurality of magnetic tunnel junctions disposed on the spin-orbit coupling layer, the plurality of magnetic tunnel junctions comprising a plurality of first magnetic tunnel junctions; the plurality of first magnetic tunnel junctions are sequentially arranged along a length direction of the spin-orbit coupling layer, and critical currents of reversals of the magnetizations of free layers of the plurality of first magnetic tunnel junctions are progressively increased or decreased in sequence along the length direction. The present disclosure provides a multi-bit memory unit with simple manufacturing process and structure.

Abstract: The present disclosure provides a multi-bit memory cell, an analog-to-digital converter, a device and a method. The multi-bit memory cell comprises: a spin-orbit coupling layer and a plurality of magnetic tunnel junctions disposed on the spin-orbit coupling layer, the plurality of magnetic tunnel junctions comprising a plurality of first magnetic tunnel junctions; the plurality of first magnetic tunnel junctions are sequentially arranged along a length direction of the spin-orbit coupling layer, and critical currents of reversals of the magnetizations of free layers of the plurality of first magnetic tunnel junctions are progressively increased or decreased in sequence along the length direction. The present disclosure provides a multi-bit memory unit with simple manufacturing process and structure.

Abstract: The present disclosure provides a magnetic random-access memory cell, a memory and a device. The magnetic random-access memory cell comprises: a spin-orbit coupling layer and a first magnetic tunnel junction and a second magnetic tunnel junction disposed on the spin-orbit coupling layer, the first magnetic tunnel junction and the second magnetic tunnel junction having at least two symmetrical axes with different lengths; an angle between an easy magnetization symmetrical axis direction of a free layer of the first magnetic tunnel junction and a length direction of the spin-orbit coupling layer is a preset first angle, and an angle between an easy magnetization symmetrical axis direction of a free layer of the second magnetic tunnel junction and the length direction of the spin-orbit coupling layer is a preset second angle; neither of the first angle and the second angle is zero degree, 90 degrees or 180 degrees.

Abstract: The present disclosure provides a magnetic random-access memory, comprising: an antiferromagnetic layer; a magnetic tunnel junction disposed on the antiferromagnetic layer and comprising a ferromagnetic layer disposed corresponding to the antiferromagnetic layer; wherein the ferromagnetic layer of the magnetic tunnel junction has in-plane magnetic anisotropy, and an exchange bias field is formed between the antiferromagnetic layer and the ferromagnetic layer by an annealing process. A direction of the exchange bias field is changed by a spin orbit torque, thereby changing a direction of a magnetic moment of the ferromagnetic layer and realizing data writing. The present disclosure can improve a thermal stability of the i-MTJ and reduce a lateral dimension of the i-MTJ, thereby improving a storage density of the magnetic memory.

Abstract: A highly reliable STT-MRAM structure and an implementation method thereof are provided. The STT-MRAM structure includes: a memory block array, including a plurality of memory blocks; on-chip in-situ temperature sensors, for detecting an instantaneous temperature of each memory block; and a controller, which outputs a reading or writing operation signal based on the instantaneous temperature of each memory block detected by the on-chip in-situ temperature sensors, so as to modulate respective voltages and/or frequencies of reading and writing operations of each memory block. When the instantaneous temperature is too high, the voltages and/or frequencies of the reading and writing operations would be decreased, to the contrary when the instantaneous temperature is too low, the voltages and/or frequencies of the reading and writing operations would be increased, which expands a reliable working temperature range and lengthens a lifetime of the STT-MRAM structure.

Abstract: A magnetic tunnel junction reference layer, magnetic tunnel junctions and a magnetic random access memory are provided, wherein the magnetic tunnel junction reference layer includes: an antiferromagnetic structure layer, which comprises a plurality of stacked metal magnetic layer units, wherein each of the metal magnetic layer units comprises a spacer layer and a magnetic layer on a surface of the spacer layer. The present invention forms a synthetic antiferromagnetic structure through multilayer stack of the metal spacer layer and the magnetic layer, so as to increase thermal stability of the magnetic tunnel junction reference layer with perpendicular magnetic anisotropy and reduce design complexity as well as cost of the film layers. The present invention forms a multilayer film structure without oxides, which has strong perpendicular magnetic anisotropy, high thermal stability, simple film layer, and low cost, thereby promoting large-scale use of the magnetic memory.

Abstract: A highly reliable STT-MRAM structure and an implementation method thereof are provided. The STT-MRAM structure includes: a memory block array, including a plurality of memory blocks; on-chip in-situ temperature sensors, for detecting an instantaneous temperature of each memory block; and a controller, which outputs a reading or writing operation signal based on the instantaneous temperature of each memory block detected by the on-chip in-situ temperature sensors, so as to modulate respective voltages and/or frequencies of reading and writing operations of each memory block. When the instantaneous temperature is too high, the voltages and/or frequencies of the reading and writing operations would be decreased, to the contrary when the instantaneous temperature is too low, the voltages and/or frequencies of the reading and writing operations would be increased, which expands a reliable working temperature range and lengthens a lifetime of the STT-MRAM structure.