Patents by Inventor Kailash Digari
Kailash Digari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10430302Abstract: An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The logic block includes multiple retention-relevant storage devices to store first data and second data. The multiple retention-relevant storage devices include a first group of retention-relevant storage devices to store the first data and a second group of retention-relevant storage devices to store the second data. The memory block maintains memory data in the memory block during a retention operational mode. The retention control circuitry causes the retention-relevant storage devices of the second group to be activated into multiple scan chains and also migrates the second data between the second group and the memory block using the multiple scan chains to accommodate transitions between the retention operational mode and a regular operational mode.Type: GrantFiled: April 12, 2017Date of Patent: October 1, 2019Assignee: QUALCOMM IncorporatedInventors: Kalyan Kumar Oruganti, Kailash Digari, Sandeep Nellikatte Srivatsa
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Patent number: 10331532Abstract: Aspects disclosed herein relate to periodic non-intrusive diagnosis of lockstep systems. An exemplary method includes comparing execution of a program on a first processing system of the plurality of processing systems and execution of the program on a second processing system of the plurality of processing systems using a first comparator circuit, comparing the execution of the program on the first processing system and the execution of the program on the second processing system using a second comparator circuit, and running a diagnosis program on the second comparator circuit while the comparing using the first comparator circuit is ongoing.Type: GrantFiled: January 19, 2017Date of Patent: June 25, 2019Assignee: QUALCOMM IncorporatedInventors: Kapil Bansal, Kailash Digari, Rahul Gulati
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Patent number: 10162922Abstract: A computer-implemented method for generating a circuit design is provided according to certain aspects. The method includes determining a gating efficiency of first gate-enable logic, determining a gating efficiency of second gate-enable logic, and determining one of the first gate-enable logic and the second gate-enable logic having a greater one of the determined gating efficiencies. The method also includes placing the determined one of the first gate-enable logic and the second gate-enable logic in clock gating logic of the circuit design, and placing another one of the first gate-enable logic and the second gate-enable in data gating logic of the circuit design.Type: GrantFiled: March 15, 2017Date of Patent: December 25, 2018Assignee: QUALCOMM IncorporatedInventors: Kalyan Kumar Oruganti, Kailash Digari, Sandeep Nellikatte Srivatsa
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Publication number: 20180300208Abstract: An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The logic block includes multiple retention-relevant storage devices to store first data and second data. The multiple retention-relevant storage devices include a first group of retention-relevant storage devices to store the first data and a second group of retention-relevant storage devices to store the second data. The memory block maintains memory data in the memory block during a retention operational mode. The retention control circuitry causes the retention-relevant storage devices of the second group to be activated into multiple scan chains and also migrates the second data between the second group and the memory block using the multiple scan chains to accommodate transitions between the retention operational mode and a regular operational mode.Type: ApplicationFiled: April 12, 2017Publication date: October 18, 2018Inventors: Kalyan Kumar Oruganti, Kailash Digari, Sandeep Nellikatte Srivatsa
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Publication number: 20180268088Abstract: A computer-implemented method for generating a circuit design is provided according to certain aspects. The method includes determining a gating efficiency of first gate-enable logic, determining a gating efficiency of second gate-enable logic, and determining one of the first gate-enable logic and the second gate-enable logic having a greater one of the determined gating efficiencies. The method also includes placing the determined one of the first gate-enable logic and the second gate-enable logic in clock gating logic of the circuit design, and placing another one of the first gate-enable logic and the second gate-enable in data gating logic of the circuit design.Type: ApplicationFiled: March 15, 2017Publication date: September 20, 2018Inventors: Kalyan Kumar Oruganti, Kailash Digari, Sandeep Nellikatte Srivatsa
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Publication number: 20180203778Abstract: Aspects disclosed herein relate to periodic non-intrusive diagnosis of lockstep systems. An exemplary method includes comparing execution of a program on a first processing system of the plurality of processing systems and execution of the program on a second processing system of the plurality of processing systems using a first comparator circuit, comparing the execution of the program on the first processing system and the execution of the program on the second processing system using a second comparator circuit, and running a diagnosis program on the second comparator circuit while the comparing using the first comparator circuit is ongoing.Type: ApplicationFiled: January 19, 2017Publication date: July 19, 2018Inventors: Kapil BANSAL, Kailash DIGARI, Rahul GULATI
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Patent number: 9396790Abstract: A multi-supply dual port register file is disclosed. The register file may be used for transferring data between two power domains that operate on different voltages or frequencies. The register file comprises a memory cell that stores the data transferred between the domains. The memory cell may be independently supplied by a reference voltage independent of that of the memory periphery. A write power domain write data to the memory cell in accordance with its operating voltage and frequency and an independent read power domain may read data from the memory cell in accordance with its independent operating voltage and frequency. The register file facilitates efficient crossing between the read and write power domains.Type: GrantFiled: June 30, 2015Date of Patent: July 19, 2016Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Amit Chhabra, Kailash Digari
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Patent number: 8112466Abstract: An efficient implementation of DSP functions in a field programmable gate array (FPGA) using one or more computational blocks, each block having of a multiplier, an accumulator, and multiplexers. The structure implements most common DSP equations in a fast and a highly compact manner. A novel method for cascading these blocks with the help of dedicated DSP lines is provided, which leads to a very simple and proficient implementation of n-stage MAC operations.Type: GrantFiled: September 28, 2005Date of Patent: February 7, 2012Assignee: Sicronic Remote KG, LLCInventors: Deboleena Minz, Kailash Digari
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Patent number: 7961004Abstract: A FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.Type: GrantFiled: December 22, 2009Date of Patent: June 14, 2011Assignee: Sicronic Remote KG, LLCInventors: Deboleena Minz, Kailash Digari
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Patent number: 7755387Abstract: An improved FPGA having a direct interconnect structure to provide selective data routing without stressing the general-purpose routing resources and to enable high rate of data exchange within the FPGA. At least two IP cores are connected to each other through the direct interconnect structure to enable simultaneous data interaction among the ports of the IP cores and to provide configurable bus width routing between the IP cores, and a plurality of logic blocks connected to the IP cores through the direct interconnect structure to enable simultaneous data routing among the IP cores and the plurality of logic blocks.Type: GrantFiled: November 1, 2005Date of Patent: July 13, 2010Assignee: Sicronic Remote KG, LLCInventors: Deboleena Minz, Kailash Digari
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Patent number: 7755388Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a domain comprising a plurality of routing lines and an input line connected to a first routing line in the domain. A switch box is connected to the first routing line and is configured to indirectly connect the input line to the other routing lines in the domain. In some embodiments a domain includes programmable switches that are configured to connect a routing line of one domain to any routing line of the other domains.Type: GrantFiled: June 12, 2008Date of Patent: July 13, 2010Inventors: Nitin Deshmukh, Kailash Digari
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Patent number: 7750673Abstract: An improved interconnect structure in programmable devices gives a new dimension to the routing architecture, where architecture is divided into various domains. It includes at least one set of input lines, each set having predetermined number of input lines; an equal number of sets of routing lines, each set of routing lines being connected to a corresponding set of input lines using a switch box; thereby forming domain based routing structures, each domain being disjoint with the other domain. Segregating FPGA routing resources into various independent routing domains is done; each domain providing connectivity to route a signal to a set of sinks.Type: GrantFiled: October 27, 2005Date of Patent: July 6, 2010Inventors: Manuj Ayodhyawasi, Kailash Digari
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Publication number: 20100097099Abstract: A FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.Type: ApplicationFiled: December 22, 2009Publication date: April 22, 2010Inventors: Deboleena Minz, Kailash Digari
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Publication number: 20080258764Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a domain comprising a plurality of routing lines and an input line connected to a first routing line in the domain. A switch box is connected to the first routing line and is configured to indirectly connect the input line to the other routing lines in the domain. In some embodiments a domain includes programmable switches that are configured to connect a routing line of one domain to any routing line of the other domains.Type: ApplicationFiled: June 12, 2008Publication date: October 23, 2008Applicant: Sicronic Remote KG, LLCInventors: Nitin Deshmukh, Kailash Digari
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Patent number: 7414433Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.Type: GrantFiled: December 7, 2007Date of Patent: August 19, 2008Assignee: Sicronic Remote KG, LLCInventors: Nitin Deshmukh, Kailash Digari
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Publication number: 20080084230Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.Type: ApplicationFiled: December 7, 2007Publication date: April 10, 2008Applicant: STMicroelectronics PVT. LTDInventors: Nitin Deshmukh, Kailash Digari
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Patent number: 7307452Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.Type: GrantFiled: October 25, 2005Date of Patent: December 11, 2007Assignee: STMicroelectronics Pvt. Ltd.Inventors: Nitin Deshmukh, Kailash Digari
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Publication number: 20060139055Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.Type: ApplicationFiled: October 25, 2005Publication date: June 29, 2006Applicant: STMicroelectronics PVT. LTD.Inventors: Nitin Deshmukh, Kailash Digari
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Publication number: 20060119388Abstract: An improved FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.Type: ApplicationFiled: November 1, 2005Publication date: June 8, 2006Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Deboleena Minz, Kailash Digari
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Publication number: 20060087342Abstract: An improved interconnect structure in programmable devices gives a new dimension to the routing architecture, where architecture is divided into various domains. It includes at least one set of input lines, each said set having predetermined number of input lines; an equal number of sets of routing lines, each said set of routing lines being connected to a corresponding set of input lines using a switch box; thereby forming domain based routing structures, each domain being disjoint with the other domain. Segregating FPGA routing resources into various independent routing domains is done; each domain providing connectivity to route a signal to a set of sinks.Type: ApplicationFiled: October 27, 2005Publication date: April 27, 2006Inventors: Manuj Ayodhyawasi, Kailash Digari