Abstract: The present invention is an efficient system and method for flexible masking of output bits from a counter. The maskable counter system and method of the present invention modify the chain carry fed into a counter so that any bit (or bits) of the counter may be masked. A masked bit of a maskable counter system and method is utilized to facilitate user programmable control of multiple configurations in a memory. A maskable counter system comprises a mask register (e.g., a D flip flop), a counter (e.g., a D flip flop), and a masking coordination circuit. The masking coordination circuit permits a carry in signal, a carry out signal, and a counter output bit signal to operate in a normal incrementation manner if a mask bit is not asserted and prevents the counter output bit signal from changing if the mask bit is asserted.