Abstract: According to some embodiments, at speed application of test patterns associated with a wide tester interface are enabled on a low pin count tester. For example, an integrated circuit might include a processor core to exchange information via input and output paths (e.g., the paths might be associated with a bus external to the integrated circuit). The integrated circuit might also include a cache structure to store test information and a sequencer to transfer the test information from the cache structure. According to some embodiments, a multiplexer receives sets of signals from (i) at least a portion of the bus and (ii) the sequencer. Moreover, the multiplexer might provide one of the received sets of signals to the processor core via the input paths.

Abstract: According to some embodiments, at speed application of test patterns associated with a wide tester interface are enabled on a low pin count tester.

Abstract: A scan cell design approach includes removing a formal verification property associated with a scan cell from a set of formal verification properties to create a reduced set of formal verification properties. A formal verification assumption verification process is then performed on a schematic using assumptions generated from the reduced set of formal verification properties. An output of the assumption verification process indicates whether there is a potential contention site at logic coupled to the output of the scan cell.