Abstract: A display panel and an array substrate thereof, which include a plurality of sub-pixel groups arranged in a matrix on the array substrate. Each sub-pixel group includes a plurality of sub-pixels arranged along rows and columns. Two adjacent sub-pixels in the same row have different colors, and two adjacent sub-pixels in the same column have the same color. In two adjacent rows of sub-pixels, an odd-numbered column or an even-numbered column is set as a target column. Two sub-pixels of the target column in the sub-pixel group are electrically connected to two adjacent data lines located on both sides of the target column. Two sub-pixels in an adjacent column of the target column are electrically connected to two adjacent data lines located on both sides of the target column. Thus, a risk of crosstalk is effectively reduced.

Abstract: A display panel includes a plurality of data lines, a plurality of scan lines, a plurality of share bar groups, and a plurality of pixel units. Each of the share bar groups includes a first share bar and a second share bar. Each of the pixel units includes a first thin-film transistor, a second thin-film transistor, and a share thin-film transistor. The first thin-film transistor and the second thin-film transistor are electrically connected to a same one of the data lines. The first thin-film transistor, the second thin-film transistor, and the share thin-film transistor are electrically connected to a same one of the scan lines. The share thin-film transistor is electrically connected to the second thin-film transistor and one of the share bar groups.

Abstract: A pixel circuit and a display device, which include a plurality of pixel driving modules, wherein each of the pixel driving modules includes a primary pixel control assembly including a primary switch and a primary pixel electrode, wherein the primary switch is configured to be controlled by a scan signal on a present-stage scan line to transfer a data signal on a data line to the primary pixel electrode; a secondary pixel control assembly including a secondary switch and a secondary pixel electrode, wherein the secondary switch is configured to be controlled by the scan signal on the present-stage scan line to transmit the data signal on the data line to the secondary pixel electrode; and a sharing switch configured to be controlled by a sharing scan signal on a sharing scan line to reduce the electric potential at the secondary pixel electrode.

Abstract: The present disclosure provides an array substrate and a display panel including the same. The array substrate includes a plurality of pixel units. Each of the pixel units includes a main pixel electrode, a sub-pixel electrode, a first thin film transistor (TFT) electrically connected to the sub-pixel electrode, a second TFT electrically connected to the first TFT, and a third TFT electrically connected to the main pixel electrode. The first TFT includes a first channel and a first semiconductor layer. The first channel includes two or more subchannels. The first semiconductor layer includes two or more semiconductor sublayers. Each of the semiconductor sublayers is disposed in a corresponding subchannel.

Abstract: The present disclosure provides an array substrate and a display panel including the same. The array substrate includes a plurality of pixel units. Each of the pixel units includes a main pixel electrode, a sub-pixel electrode, a first thin film transistor (TFT) electrically connected to the sub-pixel electrode, a second TFT electrically connected to the first TFT, and a third TFT electrically connected to the main pixel electrode. The first TFT includes a first channel and a first semiconductor layer. The first channel includes two or more subchannels. The first semiconductor layer includes two or more semiconductor sublayers. Each of the semiconductor sublayers is disposed in a corresponding subchannel.

Abstract: The present application discloses a display panel and a display device, which include a plurality of sub-pixels, and each of sub-pixel includes a first pixel electrode with a first pixel voltage and a second pixel electrode with a second pixel voltage; when the sub-pixels are in a low-gray-scale state, the second pixel voltage and the first pixel voltage have a first ratio; when the sub-pixels are in a high-gray-scale state, the second pixel voltage and the first pixel voltage have a second ratio, and the second ratio is greater than the first ratio.

Abstract: A pixel electrode and a display panel are provided. The pixel electrode includes a sub-pixel region and a main pixel region arranged at intervals. The sub-pixel region includes a first sub-pixel region and a second sub-pixel region, wherein a receiving chamber is formed between the first sub-pixel region and the second sub-pixel region, and the main pixel region is disposed in the receiving chamber.

Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, a thin film transistor layer disposed on the substrate, and a pixel electrode layer disposed on the thin film transistor layer. The pixel electrode layer includes a plurality of pixel regions, and the pixel regions include a first pixel region and a second pixel region. A pixel electrode in the second pixel region is disposed along an outer boundary of the first pixel region, or a pixel electrode in the first pixel region is disposed along an outer boundary of the second pixel region.

Abstract: The present application provides a liquid crystal display panel and a method of manufacturing the same. The liquid crystal display panel includes a pixel electrode and liquid crystals, wherein the pixel electrode includes a middle region and a peripheral region located at a periphery of the middle region, the liquid crystals disposed corresponding to the middle region have a first pretilt angle, the liquid crystals disposed corresponding to the peripheral region have a second pretilt angle, and the first pretilt angle is greater than the second pretilt angle.

Abstract: A pixel electrode and a display panel are provided. The pixel electrode includes a sub-pixel region and a main pixel region arranged at intervals. The sub-pixel region includes a first sub-pixel region and a second sub-pixel region, wherein a receiving chamber is formed between the first sub-pixel region and the second sub-pixel region, and the main pixel region is disposed in the receiving chamber.

Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, a thin film transistor layer disposed on the substrate, and a pixel electrode layer disposed on the thin film transistor layer. The pixel electrode layer includes a plurality of pixel regions, and the pixel regions include a first pixel region and a second pixel region. A pixel electrode in the second pixel region is disposed along an outer boundary of the first pixel region, or a pixel electrode in the first pixel region is disposed along an outer boundary of the second pixel region.

Abstract: The present application provides a liquid crystal display panel and a method of manufacturing the same. The liquid crystal display panel includes a pixel electrode and liquid crystals, wherein the pixel electrode includes a middle region and a peripheral region located at a periphery of the middle region, the liquid crystals disposed corresponding to the middle region have a first pretilt angle, the liquid crystals disposed corresponding to the peripheral region have a second pretilt angle, and the first pretilt angle is greater than the second pretilt angle.