Patents by Inventor Kailiang Chen
Kailiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9778348Abstract: Circuitry for ultrasound devices is described. A multilevel pulser is described, which can provide bipolar pulses of multiple levels. The multilevel pulser includes a pulsing circuit and pulser and feedback circuit. Symmetric switches are also described. The symmetric switches can be positioned as inputs to ultrasound receiving circuitry to block signals from the receiving circuitry.Type: GrantFiled: March 31, 2016Date of Patent: October 3, 2017Assignee: Butterfly Network, Inc.Inventors: Kailiang Chen, Tyler S. Ralston, Keith G. Fife
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Publication number: 20170264307Abstract: An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.Type: ApplicationFiled: May 25, 2017Publication date: September 14, 2017Applicant: Butterfly Network, Inc.Inventors: Kailiang Chen, Tyler S. Ralston
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Patent number: 9705518Abstract: An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.Type: GrantFiled: December 2, 2015Date of Patent: July 11, 2017Assignee: Butterfly Network, Inc.Inventors: Kailiang Chen, Tyler S. Ralston
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BIASING OF CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCERS (CMUTS) AND RELATED APPARATUS AND METHODS
Publication number: 20170157646Abstract: Electrical biasing of ultrasonic transducers of an ultrasound device is described. The ultrasonic transducers may be capacitive micromachined ultrasonic transducers (CMUTs). The ultrasonic transducers may be grouped together, with the different groups receiving different bias voltages. The bias voltages for the various groups of ultrasonic transducers may be selected to account for differences between the groups.Type: ApplicationFiled: December 2, 2015Publication date: June 8, 2017Applicant: Butterfly Network, Inc.Inventors: Susan A. Alie, Jaime Scott Zahorian, Kailiang Chen -
Publication number: 20170160387Abstract: Apparatus and methods are provided directed to a device, including at least one ultrasonic transducer, a multi-level pulser coupled to the at least one ultrasonic transducer; the multi-level pulser including a plurality of input terminals configured to receive respective input voltages, an output terminal configured to provide an output voltage, and a signal path between a first input terminal and the output terminal including a first transistor having a first conductivity type coupled to a first diode and, in parallel, a second transistor having a second conductivity type coupled to a second diode.Type: ApplicationFiled: October 7, 2016Publication date: June 8, 2017Applicant: Butterfly Network, Inc.Inventors: Kailiang Chen, Tyler S. Ralston
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Publication number: 20170163225Abstract: A variable current trans-impedance amplifier (TIA) for an ultrasound device is described. The TIA may be coupled to an ultrasonic transducer to amplify an output signal of the ultrasonic transducer representing an ultrasound signal received by the ultrasonic transducer. During acquisition of the ultrasound signal by the ultrasonic transducer, one or more current sources in the TIA may be varied.Type: ApplicationFiled: December 2, 2015Publication date: June 8, 2017Applicant: Butterfly Network, Inc.Inventors: Kailiang Chen, Keith G. Fife, Nevada J. Sanchez, Andrew J. Casper, Tyler S. Ralston
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Publication number: 20170163276Abstract: An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.Type: ApplicationFiled: December 2, 2015Publication date: June 8, 2017Applicant: Butterfly Network, Inc.Inventors: Kailiang Chen, Tyler S. Ralston
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Publication number: 20170160388Abstract: Methods and apparatus are described for implementing a coding scheme on ultrasound signals received by a plurality of ultrasonic transducers. The coding, and subsequent decoding, may allow for multiple ultrasonic transducers to be operated in a receive mode simultaneously while still differentiating the contribution of the individual ultrasonic transducers. Improved signal characteristics may result, including improved signal-to-noise ratio (SNR).Type: ApplicationFiled: December 2, 2015Publication date: June 8, 2017Applicant: Butterfly Network, Inc.Inventors: Kailiang Chen, Keith G. Fife, Tyler S. Ralston, Nevada J. Sanchez, Andrew J. Casper
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Publication number: 20170160239Abstract: An ultrasound device, including a profile generator, an encoder configured to receive a profile signal from the profile generator, and an attenuator configured to receive a signal representing an output of an ultrasound sensor and coupled to the encoder to receive a control signal from the encoder, the attenuator including a plurality of attenuator stages, the attenuator configured to produce an output signal that is an attenuated version of the input signal.Type: ApplicationFiled: December 2, 2015Publication date: June 8, 2017Applicant: Butterfly Network, Inc.Inventors: Kailiang Chen, Tyler S. Ralston
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Patent number: 9492144Abstract: Apparatus and methods are provided directed to a device, including at least one ultrasonic transducer, a multi-level pulser coupled to the at least one ultrasonic transducer; the multi-level pulser including a plurality of input terminals configured to receive respective input voltages, an output terminal configured to provide an output voltage, and a signal path between a first input terminal and the output terminal including a first transistor having a first conductivity type coupled to a first diode and, in parallel, a second transistor having a second conductivity type coupled to a second diode.Type: GrantFiled: December 2, 2015Date of Patent: November 15, 2016Assignee: Butterfly Network, Inc.Inventors: Kailiang Chen, Tyler S. Ralston
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Patent number: 9473136Abstract: Apparatus and methods are provided directed to a device, including at least one ultrasonic transducer, a level shifter coupled to the at least one ultrasonic transducer, the level shifter including an input terminal configured to receive an input voltage, an output terminal configured to provide an output voltage level-shifted from the input voltage, a capacitor coupled between the input terminal and the output terminal, and a diode coupled in reverse-biased configuration between an input to an active high voltage element and a first voltage of a high voltage power supply.Type: GrantFiled: December 2, 2015Date of Patent: October 18, 2016Inventors: Kailiang Chen, Tyler S. Ralston
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APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH COLUMN-ROW-PARALLEL ARCHITECTURE FOR ULTRASONIC IMAGING
Publication number: 20150087991Abstract: An ultrasonic imaging system is described in which a column-row-parallel architecture is provided at the circuit level of an ultrasonic transceiver. The ultrasonic imaging system can include a N×M array of transducer elements and a plurality of transceiver circuits where each transceiver circuit is connected to a corresponding one transducer element of the N×M array of transducer elements. A shared pulser gate driver and a shared VGA is provided for each row and column. Selection logic includes row select, column select, and per-element bit select. Through the column-row-parallel architecture, a variety of aperture configurations can be achieved.Type: ApplicationFiled: September 25, 2014Publication date: March 26, 2015Inventors: Kailiang Chen, Charles G. Sodini -
Patent number: 8742794Abstract: A distributed, reconfigurable statistical signal processing apparatus comprises an array of discrete-time analog signal processing circuitry for statistical signal processing based on a local message-passing algorithm and digital configuration circuitry for controlling the functional behavior of the array of analog circuitry. The input signal to the apparatus may be expressed as a probabilistic representation. The analog circuitry may comprise computational elements arranged in a network, with a receiving module that assigns probability values when an input signal arrives and communicates the probability values to one of the computational elements, the computational elements producing outputs based on the assigned probability values. The signal processing apparatus may be an analog logic automata cell or an array of cells, wherein each cell is able to communicate with all neighboring cells.Type: GrantFiled: April 13, 2009Date of Patent: June 3, 2014Assignee: Massachusetts Institute of TechnologyInventors: Neil Gershenfeld, Kailiang Chen, Jonathan Leu
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Patent number: 8692575Abstract: A family of self-timed, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level. The elements pass information by means of state tokens, rather than voltages. Each cell is self-timed, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, the edges receiving state tokens from neighboring logic elements and transferring output state tokens to neighboring logic elements, and circuitry configured to perform, when the circuitry inputs contain valid tokens and the circuitry outputs are empty, a logic operation utilizing received tokens as inputs, thereby producing an output token reflecting the result of the logic operation.Type: GrantFiled: October 11, 2011Date of Patent: April 8, 2014Assignee: Massachusetts Institute of TechnologyInventors: Neil Gershenfeld, Kailiang Chen, David Allen Dalrymple
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Patent number: 8350614Abstract: A distributed, reconfigurable statistical signal processing apparatus comprises an array of discrete-time analog signal processing circuitry for statistical signal processing based on a local message-passing algorithm and digital configuration circuitry for controlling the functional behavior of the array of analog circuitry. The input signal to the apparatus may be expressed as a probabilistic representation. The analog circuitry may comprise computational elements arranged in a network, with a receiving module that assigns probability values when an input signal arrives and communicates the probability values to one of the computational elements, the computational elements producing outputs based on the assigned probability values. The signal processing apparatus may be an analog logic automata cell or an array of cells, wherein each cell is able to communicate with all neighboring cells.Type: GrantFiled: April 13, 2009Date of Patent: January 8, 2013Assignee: Massachusetts Institute of TechnologyInventors: Neil Gershenfeld, Kailiang Chen, Jonathan Leu
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Publication number: 20120025868Abstract: A family of self-timed, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level. The elements pass information by means of state tokens, rather than voltages. Each cell is self-timed, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, the edges receiving state tokens from neighboring logic elements and transferring output state tokens to neighboring logic elements, and circuitry configured to perform, when the circuitry inputs contain valid tokens and the circuitry outputs are empty, a logic operation utilizing received tokens as inputs, thereby producing an output token reflecting the result of the logic operation.Type: ApplicationFiled: October 11, 2011Publication date: February 2, 2012Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Neil Gershenfeld, Kailiang Chen, David Allen Dalrymple
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Patent number: 8035414Abstract: A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation.Type: GrantFiled: April 13, 2009Date of Patent: October 11, 2011Assignee: Massachusetts Institute of TechnologyInventors: Neil Gershenfeld, Kailiang Chen, David Allen Dalrymple
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Publication number: 20100102848Abstract: A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation.Type: ApplicationFiled: April 13, 2009Publication date: April 29, 2010Applicant: Massachusetts Institute of TechnologyInventors: Neil Gershenfeld, Kailiang Chen, David Allen Dalrymple
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Publication number: 20100033228Abstract: A distributed, reconfigurable statistical signal processing apparatus comprises an array of discrete-time analog signal processing circuitry for statistical signal processing based on a local message-passing algorithm and digital configuration circuitry for controlling the functional behavior of the array of analog circuitry. The input signal to the apparatus may be expressed as a probabilistic representation. The analog circuitry may comprise computational elements arranged in a network, with a receiving module that assigns probability values when an input signal arrives and communicates the probability values to one of the computational elements, the computational elements producing outputs based on the assigned probability values. The signal processing apparatus may be an analog logic automata cell or an array of cells, wherein each cell is able to communicate with all neighboring cells.Type: ApplicationFiled: April 13, 2009Publication date: February 11, 2010Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Neil Gershenfeld, Kailiang Chen, Jonathan Leu