Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

Abstract: Methods, systems, and devices for support structures for tier deflection in a memory system are described. The memory system may include a word line contact that extends through a stack of materials and lands on a tier of a word line. The word line contact may be between four support structures that form a diamond around the word line contact. Two support structures that form opposite vertices of the diamond may align centrally with the word line contact in a lateral direction and two other support structures that form opposite vertices of the diamond may align centrally with the word line contact in a longitudinal direction.

Abstract: Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of slit structures extends through the stack structure and divides the stack structure into a series of blocks. In a progressed portion of the series of blocks, each block comprises an array of pillars extending through the stack structure of the block. Also, each block—in the progressed portion—has a different block width than a block width of a neighboring block of the progressed portion of the series of blocks. At least one pillar, of the pillars of the array of pillars in the progressed portion, exhibits bending. Related methods and electronic systems are also disclosed.

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

Abstract: Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of slit structures extends through the stack structure and devices the stack structure into a series of blocks. In a progressed portion of the series of blocks, each block comprises an array of pillars extending the through the stack structure of the block. Also, each block—in the progressed portion—has a different block width than a block width of a neighboring block of the progressed portion of the series of blocks. At least one pillar, of the pillars of the array of pillars in the progressed portion, exhibits bending. Related methods and electronic systems are also disclosed.

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

Abstract: Provided is an accurate load shedding system and method based on a power-dedicated wireless network. The system includes: a control master station layer, a control substation layer and a terminal user access layer. The control master station layer includes a control master station apparatus and an optical/E1 conversion device. The control substation layer includes an optical/E1 conversion device, a control substation apparatus and a wireless access device. The terminal user access layer includes a wireless core network, a base station and a control terminal. The wireless access device is connected to the wireless core network through Ethernet. The wireless core network is connected with the base station through an optical fiber. The control terminal is connected to a wireless network of the base station through customer premise equipment (CPE).

Abstract: Provided is an emergency accurate control method and system for large-scale interruptible loads. The method includes: acquiring, by a region control master station, a sheddable load sequence table; acquiring, by the region control master station, a first to-be-shed load; performing, by the region control master station, minimum under-shedding matching layer by layer according to the first to-be-shed load, and shedding a sheddable load corresponding to control substation matching with the first to-be-shed load; and sending, by the region control master station, a second to-be-shed load to the corresponding control substation for load shedding if the second to-be-shed load exists.

Abstract: Provided are an accurate load shedding system, and a communication method and an access apparatus thereof. The access apparatus includes: two E1 interfaces, eight optical fiber interfaces, a CPU and an FPGA. The two E1 interfaces are respectively connected to a control apparatus A and a control apparatus B of a control substation. The eight optical fiber interfaces are respectively connected to eight control terminals. The FPGA includes eight optical fiber transceivers respectively connected to the eight optical fiber interfaces through serial interfaces, and two E1 transceivers respectively connected to the two E1 interfaces through serial interfaces. Each optical fiber transceiver includes a reset submodule. Each E1 transceiver also includes a reset submodule. The CPU is connected to the FPGA through a parallel bus.

Abstract: Provided are a method, master station and system for processing parameters of grid-load terminal. The method includes: receiving parameter information uploaded by at least one grid-load terminal, where the parameter information includes at least one of a user line parameter, a control parameter, a user configuration parameter, an acquisition parameter and a description parameter corresponding to the grid-load terminal; comparing the parameter information with user profile parameter information stored in the master station; and modifying inconsistent parameters in the user profile parameter information according to the parameter information if the parameter information is inconsistent with the user profile parameter information stored in the master station.

Abstract: Provided is an emergency accurate control method and system for large-scale interruptible loads. The method includes: acquiring, by a region control master station, a sheddable load sequence table; acquiring, by the region control master station, a first to-be-shed load; performing, by the region control master station, minimum under-shedding matching layer by layer according to the first to-be-shed load, and shedding a sheddable load corresponding to control substation matching with the first to-be-shed load; and sending, by the region control master station, a second to-be-shed load to the corresponding control substation for load shedding if the second to-be-shed load exists.

Abstract: Provided is an accurate load shedding system and method based on a power-dedicated wireless network. The system includes: a control master station layer, a control substation layer and a terminal user access layer. The control master station layer includes a control master station apparatus and an optical/E1 conversion device. The control substation layer includes an optical/E1 conversion device, a control substation apparatus and a wireless access device. The terminal user access layer includes a wireless core network, a base station and a control terminal. The wireless access device is connected to the wireless core network through Ethernet. The wireless core network is connected with the base station through an optical fiber. The control terminal is connected to a wireless network of the base station through customer premise equipment (CPE).

Abstract: Provided are an accurate load shedding system, and a communication method and an access apparatus thereof. The access apparatus includes: two E1 interfaces, eight optical fiber interfaces, a CPU and an FPGA. The two E1 interfaces are respectively connected to a control apparatus A and a control apparatus B of a control substation. The eight optical fiber interfaces are respectively connected to eight control terminals. The FPGA includes eight optical fiber transceivers respectively connected to the eight optical fiber interfaces through serial interfaces, and two E1 transceivers respectively connected to the two E1 interfaces through serial interfaces. Each optical fiber transceiver includes a reset submodule. Each E1 transceiver also includes a reset submodule. The CPU is connected to the FPGA through a parallel bus.

Abstract: Provided are a synchronization method, a wide area system protection apparatus, a plant station and a computer readable storage medium. The method includes: sending to a second plant station a first data frame that includes a sequence number p and a sending timestamp of the first data frame; receiving a second data frame sent by the second plant station, and recording a receiving timestamp of the second data frame, the second data frame including a sequence number q of the second data frame, a sending timestamp of the second data frame and a receiving timestamp of the first data frame, and the first data frame being adjacent to the second frame on the second plant station; calculating a time phase difference and a crystal oscillator frequency deviation between the first plant station and the second plant station; and adjusting time and a clock frequency of the first plant station.