Abstract: The present invention discloses a method for viewing simulation signals of digital products and a simulation system, the method includes: when performing FPGA simulation on digital products, reading out all external port status data of digital products in real time and recording, meanwhile reading out all internal status data of digital products once every interval time and recording; after completing the simulation, when needing a back trace to check the data of digital products in a certain clock cycle, reading out the internal status data of digital products stored at the last time point before this clock cycle and the external port status data at said time point in the recorded simulation data; and taking the read-out data as an initial status data of the FPGA, then reading out all internal status data of digital products clock by clock until running to the clock cycle that needs to be viewed.

Abstract: The present invention discloses a method for external devices accessing computer memory, which includes: the external device applying to a computer for a memory space with a certain size, and receiving multiple memory blocks fed back by the computer; the external device establishing a memory mapping relation between the external device and the computer by means of a sequential storage structure or a chain storage structure; and when initiating a read-and-write operation, the external device finding the corresponding offset address in said computer according to the memory mapping relation between the external device and the computer, generating a read-and-write burst command, and actualizing read-and-write operations in the computer memory. The present invention can achieve the rapid and continuous access to multiple discontinuous memory areas of the computer memory, and improve the speed in the computer’s operating system and external devices accessing the memory.

Abstract: The present invention discloses a method and system for processing simulation data. The method includes: simultaneously collecting the simulation waveform data of said multiple FPGAs and adding a time stamp to the waveform data of each FPGA collected in each collection period, and storing the waveform data of the multiple FPGAs in the form of a link list according to the time stamp. The technical solution of the present invention can ensure no disorder of the waveform data of multiple FPGAs.

Abstract: The present invention discloses a method and system for viewing simulation signals of a digital product. When a controller controls a FPGA to perform a first simulation verification, the controller reads and records status data of all external ports of the digital product in real time, and reads and records all internal status data of the digital product once at each interval. After the FPGA simulation is completed, if data of a certain clock cycle of the digital product needs to be viewed in a backtracking manner, the controller loads the digital product into the software simulator to perform a second simulation verification, and sets the external port status data and the internal status data recorded at said last time point as an initial status of the digital product. By adopting the technical solution, all simulated data of any clock cycle can be viewed quickly in a backtracking manner.

Abstract: The present invention discloses a simulation signal viewing method and system for a digital product. Firstly, a controller controls a FPGA to perform a first simulation verification by reading and recording status data of all external ports of the digital product in real time, and reading and recording all internal status data of the digital product once at each interval. After the simulation is completed, if data of a certain clock cycle of the digital product needs to be viewed in a backtracking manner, the controller reads the internal status data of the digital product stored at a last time point before the certain clock cycle and the status data of the external ports at the last time point, and, using the read data as initial operating status data for a second simulation verification, starts the FPGA to operate to one clock cycle before the certain clock cycle.