Patents by Inventor Kaisheng Ma

Kaisheng Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11422818
    Abstract: The present application provides an energy management system and method, electronic device, electronic apparatus, and nonvolatile processor. The method includes: performing prediction computation based on at least one type of the received power supply information, power storage information, and power outage information of the electronic device for at least one moment, and outputting at least one of a data bitwidth instruction, a start instruction or a write strategy instruction, or/and QoS prediction information; and performing energy management on operations of the processor based on the at least one instruction, or/and the QoS prediction information. In the present application, it can be ensured that the operations of the processor is matched with the expected energy thereof, and the QoS can be matched with the minimum QoS requested in advance.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 23, 2022
    Assignee: INSTITUTE FOR INTERDISCIPLINARY INFORMATION CORE TECHNOLOGY (XI'AN) CO., LTD.
    Inventor: Kaisheng Ma
  • Patent number: 10672475
    Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS?VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 2, 2020
    Assignee: The Penn State Research Foundation
    Inventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
  • Publication number: 20200110614
    Abstract: The present application provides an energy management system and method, electronic device, electronic apparatus, and nonvolatile processor. The method includes: performing prediction computation based on at least one type of the received power supply information, power storage information, and power outage information of the electronic device for at least one moment, and outputting at least one of a data bitwidth instruction, a start instruction or a write strategy instruction, or/and QoS prediction information; and performing energy management on operations of the processor based on the at least one instruction, or/and the QoS prediction information. In the present application, it can be ensured that the operations of the processor is matched with the expected energy thereof, and the QoS can be matched with the minimum QoS requested in advance.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 9, 2020
    Inventor: Kaisheng MA
  • Publication number: 20200027508
    Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS?VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.
    Type: Application
    Filed: September 24, 2019
    Publication date: January 23, 2020
    Inventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
  • Patent number: 10475514
    Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS-VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: November 12, 2019
    Assignee: The Penn State Research Foundation
    Inventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
  • Patent number: 10324644
    Abstract: Examples described herein include receiving an operation pipeline for a computing system and building a graph that comprises a model for a number of potential memory side accelerator thread assignments to carry out the operation pipeline. The computing system may comprise at least two memories and a number of memory side accelerators. Each model may comprise a number of steps and at least one step out of the number of steps in each model may comprise a function performed at one memory side accelerator out of the number of memory side accelerators. Examples described herein also include determining a cost of at least one model.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 18, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Kaisheng Ma, Qiong Cai, Cong Xu, Paolo Faraboschi
  • Publication number: 20180330791
    Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS?VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 15, 2018
    Inventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
  • Publication number: 20180285011
    Abstract: Examples described herein include receiving an operation pipeline for a computing system and building a graph that comprises a model for a number of potential memory side accelerator thread assignments to carry out the operation pipeline. The computing system may comprise at least two memories and a number of memory side accelerators. Each model may comprise a number of steps and at least one step out of the number of steps in each model may comprise a function performed at one memory side accelerator out of the number of memory side accelerators. Examples described herein also include determining a cost of at least one model.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Kaisheng Ma, Qiong Cai, Cong Xu, Paolo Faraboschi