Abstract: A method for operating a memory device is provided. The memory device includes a first word line, a second word line, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first word line and the second word line. A first pass voltage is applied to the first dummy word line in a program operation. A second pass voltage is applied to the second dummy word line in the program operation. The first pass voltage is different from the second pass voltage.

Abstract: In certain aspects, a memory device includes memory strings each including a first drain select gate (DSG) transistor, an insulating structure disposed between two adjacent sets of the memory strings and electrically separating the first DSG transistors of the two adjacent sets of the memory strings, first DSG line, each coupled to the first DSG transistors in a respective set of the two adjacent sets of the memory strings, and a peripheral circuit coupled to the memory strings through the first DSG lines and configured to, in an operation, apply a negative voltage to an unselect first DSG line of the first DSG lines, wherein the unselect first DSG line is coupled to the first DSG transistors in an unselect set of the two adjacent sets of the memory strings.

Abstract: In some aspects, a memory device is provided. The memory device includes a plurality of memory strings and a peripheral circuit. One of the memory strings includes memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells. The peripheral circuit is coupled to the memory strings and configured to, in a pre-pulse period of a program operation, maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell. After applying the second voltage to the dummy word line, the peripheral circuit is further configured to apply a third voltage to the select line to turn off the select transistor.

Abstract: A semiconductor device includes a memory string including a first memory cell, a second memory cell, and a third memory cell between the first memory cell and the second memory cell, word lines including a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, a third word line coupled to the third memory cell, and a peripheral circuit coupled to the word lines. The peripheral circuit is configured to in a programming phase, apply a first pass voltage to the second word line, and after applying the first pass voltage to the second word line, apply a programming voltage to the first word line to program the first memory cell.

Abstract: In some aspects, a memory device is provided. The memory device includes a plurality of memory strings and a peripheral circuit. One of the memory strings includes memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells. The peripheral circuit is coupled to the memory strings and configured to, in a pre-pulse period of a program operation, maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell. After applying the second voltage to the dummy word line, the peripheral circuit is further configured to apply a third voltage to the select line to turn off the select transistor.

Abstract: A data processing method applied to a graph database, includes: determining each to-be-queried object in a received query statement and a screening condition for each to-be-queried object based on the query statement, wherein the to-be-queried object includes at least one of a graph data vertex or a graph data edge in the graph database; generating a target node corresponding to each to-be-queried object, performing semantic analysis on the screening condition for the to-be-queried object, determining a semantic query condition, and determining a sub-node of the target node based on each determined semantic query condition; determining, based on a sub-node of each target node, each database operation corresponding to the target node that needs to be performed by the graph database; and executing a data processing task corresponding to the query statement based on each database operation, and returning an execution result based on the query statement.

Abstract: A programming method and a semiconductor device are provided. The semiconductor device includes a memory string that includes a plurality of first memory cells and a first dummy cell stacked in sequence, and each first memory cell is connected to a respective word line, and a gate of the first dummy cell is connected to a first dummy word line. The method includes: in a programming phase, applying a first pass voltage to a word line corresponding to a first unprogrammed memory cell, wherein the first unprogrammed memory cell is an unprogrammed memory cell of the plurality of first memory cells separated from a to-be-programmed memory cell by a first preset number of first memory cells; and after applying the first pass voltage to the word line corresponding to the first unprogrammed memory cell, applying a programming voltage to the word line corresponding to the to-be-programmed memory cell.

Abstract: An electrocardiograph (ECG) signal detection and positioning method based on weakly supervised learning is provided. A deep learning model mainly includes a multi-scale feature extraction module, a self-attention encoding module, and a classification and positioning module. An extracted original ECG signal is denoised and segmented to obtain a fixed-length pure ECG signal segment. In the convolutionally-connected multi-scale feature extraction module, a channel local attention (CLA) layer is introduced, and a PReLU activation function is used to achieve a better local information extraction capability. The self-attention encoding module is introduced to establish an association between a local feature and a global feature. The classification and positioning module is introduced to output a general location of an abnormal signal. A fusion module enables the model to map a local predicted value onto a global predicted value, and model parameters are trained on a weakly annotated dataset.

Abstract: A memory device includes a memory string and a control circuit. The memory string includes a top select gate, a memory cell, and a bottom select gate. The top select gate is coupled to a first select line, the memory cell is coupled to a word line, and the bottom select gate is coupled to a second select line. The control circuit is coupled to the first select line, the word line, and the second select line.

Abstract: An electrocardiograph (ECG) signal detection and positioning method based on weakly supervised learning is provided. A deep learning model mainly includes a multi-scale feature extraction module, a self-attention encoding module, and a classification and positioning module. An extracted original ECG signal is denoised and segmented to obtain a fixed-length pure ECG signal segment. In the convolutionally-connected multi-scale feature extraction module, a channel local attention (CLA) layer is introduced, and a PReLU activation function is used to achieve a better local information extraction capability. The self-attention encoding module is introduced to establish an association between a local feature and a global feature. The classification and positioning module is introduced to output a general location of an abnormal signal. A fusion module enables the model to map a local predicted value onto a global predicted value, and model parameters are trained on a weakly annotated dataset.

Abstract: Implementations of the present disclosure disclose a memory operation method, a memory device, a memory system and an electronic apparatus. The memory device includes a memory stack structure, a select stack structure on the memory stack structure, a memory string including a first sub-string penetrating through the select stack structure, and a second sub-string penetrating through the memory stack structure, and including a first dummy memory cell adjacent to a plug, and a plurality of memory cells, a peripheral circuit connected with the memory string and configured to program the first dummy memory cell, and apply a first bias voltage to a first dummy word line coupled to the first dummy memory cell in a pre-charge stage of a program operation of one of the plurality of memory cells close to the plug.

Abstract: A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, and a bottom select gate. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the memory string, apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string, and apply a first turn-on voltage to the bottom select gate, before applying the verifying voltage to the at least one word line.

Abstract: A data processing method applied to a graph database, includes: determining each to-be-queried object in a received query statement and a screening condition for each to-be-queried object based on the query statement, wherein the to-be-queried object includes at least one of a graph data vertex or a graph data edge in the graph database; generating a target node corresponding to each to-be-queried object, performing semantic analysis on the screening condition for the to-be-queried object, determining a semantic query condition, and determining a sub-node of the target node based on each determined semantic query condition; determining, based on a sub-node of each target node, each database operation corresponding to the target node that needs to be performed by the graph database; and executing a data processing task corresponding to the query statement based on each database operation, and returning an execution result based on the query statement.

Abstract: The disclosure provides a three-dimensional (3D) memory, a method of fabricating a 3D memory and a memory system. The 3D memory can include a stack including alternately stacked first dielectric layers and conductive layers, and a channel structure extending through the stack and including a second dielectric layer and a blocking layer disposed in this order from outside to inside. The second dielectric layer can have a dielectric constant greater than or equal to 3.9.

Abstract: A method for operating a memory device is disclosed. The memory device includes a first word line, a second word line, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first word line and the second word line. A first pass voltage is applied to the first dummy word line in a program operation. A second pass voltage is applied to the second dummy word line in the program operation. The first pass voltage is different from the second pass voltage.

Abstract: A method for monitoring an online state of a bonding wire of an Insulated Gate Bipolar Translator (IGBT) module comprises the following steps: Step 1, constructing a full bridge inverter circuit and an online measuring circuit and connecting two input ends of the online measuring circuit to a collecting electrode and an emitting electrode of an IGBT power module of the full bridge inverter circuit to realize a connection of the full bridge inverter circuit and the online measuring circuit; Step 2, establishing a three-dimensional data model of a healthy IGBT; Step 3, establishing a three-dimensional data model of the IGBT with a broken bonding wire; Step 4, optimizing a least squares support vector machine by adopting a genetic algorithm; and Step 5, estimating states of the three-dimensional data models obtained in the Step 2 and the Step 3 by utilizing the optimized least squares support vector machine.

Abstract: A method for operating a memory is disclosed. The memory includes a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines. A first pass voltage is applied to the first dummy word line and applying a second pass voltage to the second dummy word line. A program voltage is applied to a selected word line, wherein a condition is met: a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.

Abstract: A method and system for in operando, in situ, and real-time monitoring the state of an electrochemical device, e.g. battery, is provided, which is by means of an optical fiber probe inside the electrochemical device. The method includes: shedding an input light into the optical fiber probe and detecting an output light transmitted therefrom; and determining state of health of the electrochemical device based on the output light. The determination step can be based on a change of the refractive index or of the cladding mode or the surface plasmon resonance, all derived from the output light, in the instant state compared to a prior state. The method can simultaneously detect other parameters including state of charge, temperature, pressure, strain, displacement, vibration, or gas release inside the electrochemical device. With a core mode for correction, the determination of these parameters can also realize a high accuracy.

Abstract: A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, and a bottom select gate. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the memory string, apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string, and apply a first turn-on voltage to the bottom select gate, before applying the verifying voltage to the at least one word line.

Abstract: In some aspects, a memory device is provided. The memory device includes a plurality of memory strings and a peripheral circuit. One of the memory strings includes memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells. The peripheral circuit is coupled to the memory strings and configured to, in a pre-pulse period of a program operation, maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell. After applying the second voltage to the dummy word line, the peripheral circuit is further configured to apply a third voltage to the select line to turn off the select transistor.