Abstract: A method for operating a memory device is disclosed. The memory device includes a first word line, a second word line, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first word line and the second word line. A first pass voltage is applied to the first dummy word line in a program operation. A second pass voltage is applied to the second dummy word line in the program operation. The first pass voltage is different from the second pass voltage.

Abstract: A method for monitoring an online state of a bonding wire of an Insulated Gate Bipolar Translator (IGBT) module comprises the following steps: Step 1, constructing a full bridge inverter circuit and an online measuring circuit and connecting two input ends of the online measuring circuit to a collecting electrode and an emitting electrode of an IGBT power module of the full bridge inverter circuit to realize a connection of the full bridge inverter circuit and the online measuring circuit; Step 2, establishing a three-dimensional data model of a healthy IGBT; Step 3, establishing a three-dimensional data model of the IGBT with a broken bonding wire; Step 4, optimizing a least squares support vector machine by adopting a genetic algorithm; and Step 5, estimating states of the three-dimensional data models obtained in the Step 2 and the Step 3 by utilizing the optimized least squares support vector machine.

Abstract: A method for operating a memory is disclosed. The memory includes a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines. A first pass voltage is applied to the first dummy word line and applying a second pass voltage to the second dummy word line. A program voltage is applied to a selected word line, wherein a condition is met: a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.

Abstract: A method and system for in operando, in situ, and real-time monitoring the state of an electrochemical device, e.g. battery, is provided, which is by means of an optical fiber probe inside the electrochemical device. The method includes: shedding an input light into the optical fiber probe and detecting an output light transmitted therefrom; and determining state of health of the electrochemical device based on the output light. The determination step can be based on a change of the refractive index or of the cladding mode or the surface plasmon resonance, all derived from the output light, in the instant state compared to a prior state. The method can simultaneously detect other parameters including state of charge, temperature, pressure, strain, displacement, vibration, or gas release inside the electrochemical device. With a core mode for correction, the determination of these parameters can also realize a high accuracy.

Abstract: A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, and a bottom select gate. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the memory string, apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string, and apply a first turn-on voltage to the bottom select gate, before applying the verifying voltage to the at least one word line.

Abstract: In some aspects, a memory device is provided. The memory device includes a plurality of memory strings and a peripheral circuit. One of the memory strings includes memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells. The peripheral circuit is coupled to the memory strings and configured to, in a pre-pulse period of a program operation, maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell. After applying the second voltage to the dummy word line, the peripheral circuit is further configured to apply a third voltage to the select line to turn off the select transistor.

Abstract: A method for operating a memory is disclosed. The memory includes a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines. A first pass voltage is applied to the first dummy word line and applying a second pass voltage to the second dummy word line. A program voltage is applied to a selected word line, wherein a condition is met: a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.

Abstract: A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level.

Abstract: A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, a bottom select gate, and a P-well. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the P-well, apply a verifying voltage to a selected word line of the word lines after applying the erasing voltage to the P-well, and apply a first turn-on voltage to the bottom select gate, starting after applying the erasing voltage to the P-well and before applying the verifying voltage to the selected word line.

Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.

Abstract: A method for estimating the junction temperature on-line on an insulated gate bipolar transistor (IGBT) power module, including the following steps. Estimate the junction temperature by the temperature sensitive electrical parameter method, set the space thermal model of the extended state, and apply the Kalman filter to the junction temperature estimation. The temperature sensitive electrical parameter method estimates the junction temperature of the IGBT power module in real time, selects the IGBT conduction voltage drop VCE(ON) as the temperature sensitive electrical parameter, and provides a VCE(ON) on-line measuring circuit. The power loss of the diode and IGBT and the estimated value of junction temperature obtained by the temperature sensitive electrical parameter method are taken as the input of the Kalman filter, and measurement noise and process noise are considered to obtain an optimal estimated value of junction temperature.

Abstract: A fiber-optic sensing apparatus is provided, including an outer sleeve, an optical fiber sensor arranged within the outer sleeve, and a filling medium. The optical fiber sensor is capable of detecting a change of a refractive index or a change of surface plasmon waves over an outer surface of the outer sleeve. The filling medium may have a matching refractive index with the outer sleeve and with the optical fiber sensor. The outer sleeve may be exposed directly to the outside medium, or may be coated with at least one functional film layer such as a surface plasmon resonance (SPR)-active base film layer, or a reactive film layer that is reactive to a target molecule in the outside medium.

Abstract: A fiber-optic sensing apparatus, system, and method for characterizing at least one metal ion in a solution are provided. The sensing apparatus includes a fiber-optic sensor and a controller. The sensor includes an optical fiber with tilted grating in its core, and includes a conductive and surface plasmon resonance (SPR)-active coating assembly that allows the sensor to also serve as an electrochemical working electrode. The controller is electrically connected with the sensor, configured to provide an adjustable potential such that when the coating assembly is in contact with the solution, redox reactions of each of the at least one metal ion occur on an outer surface thereof, resulting in a detectable change of the surface plasmon waves generated in the fiber-optic sensor. Based on the change thus detected, identities and/or concentration of the at least one metal ion in the solution can be determined with high accuracy and sensitivity.

Abstract: A method for monitoring an online state of a bonding wire of an Insulated Gate Bipolar Translator (IGBT) module comprises the following steps: Step 1, constructing a full bridge inverter circuit and an online measuring circuit and connecting two input ends of the online measuring circuit to a collecting electrode and an emitting electrode of an IGBT power module of the full bridge inverter circuit to realize a connection of the full bridge inverter circuit and the online measuring circuit; Step 2, establishing a three-dimensional data model of a healthy IGBT; Step 3, establishing a three-dimensional data model of the IGBT with a broken bonding wire; Step 4, optimizing a least squares support vector machine by adopting a genetic algorithm; and Step 5, estimating states of the three-dimensional data models obtained in the Step 2 and the Step 3 by utilizing the optimized least squares support vector machine.

Abstract: A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level.

Abstract: A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, a bottom select gate, and a P-well. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the P-well, apply a verifying voltage to a selected word line of the word lines after applying the erasing voltage to the P-well, and apply a first turn-on voltage to the bottom select gate, starting after applying the erasing voltage to the P-well and before applying the verifying voltage to the selected word line.

Abstract: A memory device includes a top select cell, a top dummy cell and a string of memory cells. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top select line. The top dummy cell has a control terminal coupled to a top dummy word line. The string of memory cells has control terminals coupled to respective word lines. A method operating the memory device includes prior to a program operation, applying a pre-pulse voltage to the top dummy word line, the top select line and the bit line while applying a low voltage to the word lines, and then sequentially applying the low voltage to the top dummy word line, the top select line and the bit line while applying the low voltage to the word lines.

Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells, and one or more dummy word lines respectively coupled to gate terminals of the one or more dummy memory cells. The memory device further includes a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines. To program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period.

Abstract: A memory device includes a plurality of memory blocks, and a control circuit. A selected memory block of the plurality of memory blocks comprises a top select gate, a bottom select gate, a plurality of word lines, a common-source line, and a P-well. The control circuit performs an erasing and verification method, wherein the erasing and verification method includes erasing the selected memory block during an erasing stage; and maintaining the bottom select gate to be turned on during a maintaining period before the top select gate are turned on during a verification stage.

Abstract: A memory device includes a plurality of memory blocks, and a control circuit. A selected memory block of the plurality of memory blocks comprises a top select gate, a bottom select gate, a plurality of word lines, a common-source line, and a P-well. The control circuit performs an erasing and verification method, wherein the erasing and verification method includes erasing the selected memory block during an erasing stage; and maintaining the bottom select gate to be turned on during a maintaining period before the top select gate are turned on during a verification stage.