Patents by Inventor Kaiwen Xu

Kaiwen Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250102701
    Abstract: Disclosed are a method and a device for identifying full-section excavation parameters of large-section tunnel with broken surrounding rock, which is capable of solving the problem of inaccurate arrangement of blasting hole points in tunnel excavation engineering, including following steps: establishing a three-dimensional finite element model based on a blasting section design of a tunnel; performing a simulation with the three-dimensional finite element model based on blasting design parameters to obtain blasting quality parameters; selecting a group closest to a preset quality parameter from multiple groups of the blasting design parameters as target blasting design parameters, wherein the preset quality parameter is an acceptance grade standard of the tunnel; obtaining first thermal imaging information of a first hot spot of a surface to be blasted; calibrating actual hole spacing parameters based on the first thermal imaging information and the target blasting design parameters.
    Type: Application
    Filed: October 11, 2024
    Publication date: March 27, 2025
    Inventors: Jun GAO, Zhongyi ZHANG, Xiao LIN, Xiaowei ZUO, Kaiwen LIU, Ming ZHANG, Bin ZHOU, Feng WANG, Yuxin GAO, Huiling XUE, Ling WANG, Zhengyi WANG, Xiaokai WEN, Yongtai WANG, Dan XU, Ke CHEN, Tenghui XU, Zhiguo LIU, Yongguo QI, Geng CHEN, Songzhen LI, Junlei ZHOU, Juntao KANG, Chunfeng MENG, Dongsheng XU, Linyue GAO
  • Patent number: 11099137
    Abstract: A semiconductor metrology tool inspects an area of a semiconductor wafer. The inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system renders an augmented-reality or virtual-reality (AR/VR) image of the model that shows a 3D shape of the model and provides the AR/VR image to an AR/VR viewing device for display.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: August 24, 2021
    Assignee: KLA Corporation
    Inventors: Aaron J. Rosenberg, Jonathan Iloreta, Thaddeus G. Dziura, Antonio Gellineau, Yin Xu, Kaiwen Xu, John Hench, Abhi Gunde, Andrei Veldman, Liequan Lee, Houssam Chouaib
  • Publication number: 20200393386
    Abstract: A semiconductor metrology tool inspects an area of a semiconductor wafer. The inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system renders an augmented-reality or virtual-reality (AR/VR) image of the model that shows a 3D shape of the model and provides the AR/VR image to an AR/VR viewing device for display.
    Type: Application
    Filed: August 28, 2020
    Publication date: December 17, 2020
    Inventors: Aaron J. Rosenberg, Jonathan Iloreta, Thaddeus G. Dziura, Antonio Gellineau, Yin Xu, Kaiwen Xu, John Hench, Abhi Gunde, Andrei Veldman, Liequan Lee, Houssam Chouaib
  • Patent number: 10794839
    Abstract: A semiconductor metrology tool inspects an area of a semiconductor wafer. The inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system renders an image of the model that shows a 3D shape of the model and provides the image to a device for display.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: October 6, 2020
    Assignee: KLA Corporation
    Inventors: Aaron J. Rosenberg, Jonathan Iloreta, Thaddeus G. Dziura, Antonio Gellineau, Yin Xu, Kaiwen Xu, John Hench, Abhi Gunde, Andrei Veldman, Liequan Lee, Houssam Chouaib
  • Publication number: 20200271595
    Abstract: A semiconductor metrology tool inspects an area of a semiconductor wafer. The inspected area includes a plurality of instances of a 3D semiconductor structure arranged periodically in at least one dimension. A computer system generates a model of a respective instance of the 3D semiconductor structure based on measurements collected during the inspection. The computer system renders an image of the model that shows a 3D shape of the model and provides the image to a device for display.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 27, 2020
    Inventors: Aaron J. Rosenberg, Jonathan Iloreta, Thaddeus G. Dziura, Antonio Gellineau, Yin Xu, Kaiwen Xu, John Hench, Abhi Gunde, Andrei Veldman, Liequan Lee, Houssam Chouaib