Abstract: A display panel, a manufacturing method thereof, and a display device are provided. The display panel includes a display region and a lens region, wherein the lens region comprises a common electrode and a deflection electrode arranged opposite each other, and a first liquid crystal layer arranged therebetween, the deflection electrode is configured for providing at least two different deflection voltages, and the at least two different deflection voltages are configured for deflecting the first liquid crystal layer. According to the display panel, the manufacturing method thereof and the display device in the embodiments of the present disclosure, it may drive the liquid crystals to deflect, so as to achieve the function of zooming of the camera. In addition, the camera is integrated with the display panel, so as to improve the integration level of the display device, and facilitate the utilization and the manufacturing of the display device.

Abstract: Embodiments disclosed herein are directed to a shelf and shelving system for a refrigerator door having a door liner with opposing side walls, where each side wall includes a row of ditch steps. The shelf or shelves includes a gap wall at each end of the shelf. A switch is positioned above each gap wall. Each switch includes a handle, a mounting rod and a biasing member for biasing a long component of the handle outwardly away from the gap wall such that an engagement surface of the long component will engage a ditch step and thereby secure the shelf in place within the refrigerator door. The switch is actuatable by a user to allow for vertical adjustment of the shelf along the rows of ditch steps or to remove the shelf therefrom.

Abstract: A display panel and a display device are provided. The display panel includes a first base substrate; a second base substrate opposite to the first base substrate; a liquid crystal layer between the first and second base substrates; a first alignment film at a side of the first base substrate facing the liquid crystal layer; a second alignment film at a side of the second base substrate facing the liquid crystal layer; a polarizer at a side of the first base substrate away from the liquid crystal layer; and a quarter-wave plate between the polarizer and the first base substrate. An angle between a center line of an included angle between the first alignment direction of the first alignment film and the second alignment direction of the second alignment film and a slow axis of the quarter-wave plate is in a range from 75 to 105 degrees.

Abstract: A light-emitting structure, comprising: a substrate, and a first metal layer, an insulating layer, an integrated metal layer, and an epitaxial stack, disposed above the substrate. The integrated metal layer is disposed on a surface of the second-type semiconductor layer facing away from the active region, and the integrated metal layer comprises an exposed surface on a side of the integrated metal layer facing the second-type semiconductor layer, the exposed surface being configured to electrically connect with an external driving device.

Abstract: A compound of formula (I) having the activity of inhibiting HPK1 kinase and a pharmaceutical composition comprising the compound. Also provided are the use of the compound in the prevention and/or treatment of cancers, tumors, inflammatory diseases, autoimmune diseases or immune-mediated diseases.

Abstract: Provided are a compound having the structure of formula (I) for inhibiting Wnt pathway activity, a pharmaceutical composition comprising the compound, and use of the compound in prevention and/or treatment of cancers, tumors, inflammatory diseases, autoimmune diseases, or immune-mediated diseases.

Abstract: The present disclosure provides a semiconductor epitaxial structure, including a substrate, a first-type semiconductor layer, an active region comprising at least one quantum layer, and a second-type semiconductor layer sequentially stacked on a surface of the substrate; wherein the quantum layer comprises barrier layers and potential well layers, and the barrier layers are alternately stacked with the potential well layers, and wherein the quantum layer further comprises a growth temperature transition layer between a barrier layer and a potential well layer, or an electron confinement layer between a barrier layer and a potential well layer.

Abstract: The present disclosure provides a semiconductor epitaxial structure and a manufacturing method therefor, and an LED chip. The semiconductor epitaxial structure may include a substrate, an N-type semiconductor layer, a gate elimination layer, an active layer and a P-type semiconductor layer are sequentially stacked on a surface of a substrate. Furthermore, the gate elimination layer comprises an N-type doped semiconductor layer.

Abstract: A light-emitting diode (LED) chip (2) comprises a substrate (20), an epitaxial structure (21), a transparent conductive layer (22), a passivation protective layer (23), and at least one electrode (25). The epitaxial structure (21) is disposed on the substrate (20). The transparent conductive layer (22) is disposed on the epitaxial structure (21). The transparent conductive layer (22) defines one or more first through holes (220) that extend through the transparent conductive layer (22). The passivation protective layer (23) is disposed on the transparent conductive layer (22). The passivation protective layer (23) defines one or more second through holes (230) that extend through the passivation protective layer (23). The electrode (25) is disposed on the passivation protective layer (23). The electrode (25) electrically connects the transparent conductive layer (11) through the one or more second through holes (230).

Abstract: A resource allocation method and apparatus, a readable medium, an electronic device and a program product are provided.

Abstract: Provided is a method for manufacturing a semiconductor wafer and a semiconductor wafer. The method includes: disposing a sacrificial layer on a first surface and a second surface of a patterned substrate, the patterned substrate comprising the first surface and the second surface having different normal directions; exposing the first surface by removing the first portion of the sacrificial layer disposed on the first surface; growing an original nitride buffer layer on the first surface and the second portion of the sacrificial layer; partially lifting off the second portion of the sacrificial layer disposed on the second surface such that at least one sub-portion of the second portion of the sacrificial layer remains on the second surface of the patterned substrate; and growing an epitaxial layer on the original nitride buffer layer, where a crystal surface of the epitaxial layer grows along a normal direction of the patterned substrate.

Abstract: A semiconductor wafer includes a substrate (1), a buffer layer (2) deposited on the substrate (1), and an epitaxial layer (4) above the buffer layer (2). The buffer layer (2) includes a plurality of semiconductor material layers (22) and a plurality of oxygen-doped material layers (21). The semiconductor material layers (22) and the oxygen-doped material layers (21) are deposited in an alternating arrangement on top of each other. Oxygen concentrations of the oxygen-doped material layers (21) gradually decrease along a direction from the substrate (1) to the epitaxial layer (4).

Abstract: Disclosed is a wafer or a material stack for semiconductor-based optoelectronic or electronic devices that minimizes or reduces misfit dislocation, as well as a method of manufacturing such wafer of material stack. A material stack according to the disclosed technology includes a substrate; a basis buffer layer of a first material disposed above the substrate; and a plurality of composite buffer layers disposed above the basis buffer layer sequentially along a growth direction. The growth direction is from the substrate to a last composite buffer layer of the plurality of composite buffer layers. Each composite buffer layer except the last composite buffer layer includes a first buffer sublayer of the first material, and a second buffer sublayer of a second material disposed above the first buffer sublayer. The thicknesses of the first buffer sublayers of the composite buffer layers decrease along the growth direction.

Abstract: Provided is a method for manufacturing a semiconductor wafer and a semiconductor wafer. The method includes: disposing a sacrificial layer on a first surface and a second surface of a patterned substrate, the patterned substrate comprising the first surface and the second surface having different normal directions; exposing the first surface by removing the first portion of the sacrificial layer disposed on the first surface; growing an original nitride buffer layer on the first surface and the second portion of the sacrificial layer; partially lifting off the second portion of the sacrificial layer disposed on the second surface such that at least one sub-portion of the second portion of the sacrificial layer remains on the second surface of the patterned substrate; and growing an epitaxial layer on the original nitride buffer layer, where a crystal surface of the epitaxial layer grows along a normal direction of the patterned substrate.

Abstract: A light-emitting diode (LED) device (e.g., AlGaInP LED) includes a transparent substrate, an epitaxial structure defining an isolation trench and an epitaxial structure, an insulating passivation layer, a P electrode and an N electrode. The epitaxial structure is disposed above the transparent substrate. The isolation trench divides the epitaxial structure into a first portion and a second portion. The at least one through hole extends through the first portion. At least a portion of the insulating passivation layer is disposed in the isolation trench. The P electrode is disposed above the first portion of the epitaxial structure and in the at least one through hole. The N electrode is disposed above the second portion of the epitaxial structure. A top surface of the P electrode is horizontally aligned with a top surface of the N electrode.

Abstract: According to at least some embodiments of the present disclosure, a method of manufacturing semiconductor wafers comprises: selectively growing a nitride buffer layer on a first surface of a patterned substrate, the patterned substrate including at least the first surface and a second surface; and growing an epitaxial layer on the nitride buffer layer, wherein a crystal surface of the epitaxial layer grows along a normal direction of the patterned substrate. The epitaxial layer does not include multiple crystal surfaces having different crystal growth directions that cause a stress at a junction interface where the crystal surfaces having the different crystal growth directions meet.

Abstract: A micro-LED macro transfer method, a micro-LED display device, and a method for fabricating the same are provided. In the micro-LED macro transfer method, the LED chips on an array are divided into a first plurality of LED chips and a second plurality of LED chips. An LED chip includes a first surface and a second surface. The first plurality of LED chips are configured so that their first surfaces are coupled to the first transfer substrate. The second plurality of LED chips are configured so that their second surfaces are coupled to the second transfer substrate. Accordingly, the first transfer substrate transfers the first plurality of LED chips to the first transfer substrate while the second transfer substrate transfers the second plurality of LED chips to the second transfer substrate.

Abstract: A light-emitting diode (LED) chip (2) comprises a substrate (20), an epitaxial structure (21), a transparent conductive layer (22), a passivation protective layer (23), and at least one electrode (25). The epitaxial structure (21) is disposed on the substrate (20). The transparent conductive layer (22) is disposed on the epitaxial structure (21). The transparent conductive layer (22) defines one or more first through holes (220) that extend through the transparent conductive layer (22). The passivation protective layer (23) is disposed on the transparent conductive layer (22). The passivation protective layer (23) defines one or more second through holes (230) that extend through the passivation protective layer (23). The electrode (25) is disposed on the passivation protective layer (23). The electrode (25) electrically connects the transparent conductive layer (11) through the one or more second through holes (230).

Abstract: A micro-LED macro transfer method, a micro-LED display device, and a method for fabricating the same are provided. In the micro-LED macro transfer method, the LED chips on an array are divided into a first plurality of LED chips and a second plurality of LED chips. An LED chip includes a first surface and a second surface. The first plurality of LED chips are configured so that their first surfaces are coupled to the first transfer substrate. The second plurality of LED chips are configured so that their second surfaces are coupled to the second transfer substrate. Accordingly, the first transfer substrate transfers the first plurality of LED chips to the first transfer substrate while the second transfer substrate transfers the second plurality of LED chips to the second transfer substrate.

Abstract: A light-emitting diode (LED) device and a method of producing the same are provided. The LED device comprises a first conductive layer, a second conductive layer, an active layer sandwiched between the first conductive layer and the second conductive layer and a first electrode in electrical contact with the first conductive layer. The first conductive layer has a laminate structure comprising a first conductive sub-layer, a current blocking layer, and a second conductive sub-layer. The first electrode comprises a first extended electrode in electrical contact with the first conductive sub-layer, and a second extended electrode in electrical contact with the second conductive sub-layer. The first conductive sub-layer and the second conductive sub-layer may have different depths.