Abstract: A spin-orbit torque magnetoresistive random access memory and a method of operating the same. The memory includes memory cells. Each memory cell includes: an orbital Hall layer for generating an orbital polarized current under an action of an in-plane current; an alloy material layer including an alloy material having spin Hall angles with opposite polarities and for generating spin polarized currents in opposite spin directions under an action of the in-plane current flowing through the alloy material layer and the orbital polarized current; a magnetic tunnel junction, including a magnetic free layer, a tunneling insulation layer, a magnetic pinned layer, and an antiferromagnetic layer or artificial antiferromagnetic layer. A competing spin current effect is generated by the spin polarized currents in the opposite spin directions to induce a deterministic magnetization switching of a magnetic moment of the magnetic free layer, so as to store an information in the memory cell.

Abstract: Provided are a function switchable random access memory, including: two electromagnetic portions configured to connect a current; a magnetic recording portion between the two electromagnetic portions and including a spin-orbit coupling layer and a magnetic tunnel junction; a pinning region between each of the electromagnetic portions and the magnetic recording portion; a cut-off region on a side of each of the electromagnetic portions opposite to the pinning region, the spin-orbit coupling layer is configured to generate a spin current under an action of the current; the two electromagnetic portions is configured to generate two magnetic domains with magnetization pointing in opposite directions under an action of the spin current; the magnetic tunnel junction is configured to generate a magnetic domain wall based on the two opposite magnetic domains and is configured to drive the magnetic domain wall to reciprocate under the action of the spin current.

Abstract: A method and a system for optimizing problem-solving based on probabilistic bit circuits are provided. The method includes: performing a modeling transformation on an objective problem to obtain a corresponding Hamiltonian relationship; obtaining a column Hamiltonian of said probabilistic bit circuit based on said Hamiltonian relationship; and performing parallel annealing iterations on multicolumn Hamiltonian based on row-flipping operations on said probabilistic bit circuits to obtain an updated probabilistic bit configuration, so as to achieve optimization of said problem.

Abstract: Provided are a function switchable random access memory, including: two electromagnetic portions configured to connect a current; a magnetic recording portion between the two electromagnetic portions and including a spin-orbit coupling layer and a magnetic tunnel junction; a pinning region between each of the electromagnetic portions and the magnetic recording portion; a cut-off region on a side of each of the electromagnetic portions opposite to the pinning region, the spin-orbit coupling layer is configured to generate a spin current under an action of the current; the two electromagnetic portions is configured to generate two magnetic domains with magnetization pointing in opposite directions under an action of the spin current; the magnetic tunnel junction is configured to generate a magnetic domain wall based on the two opposite magnetic domains and is configured to drive the magnetic domain wall to reciprocate under the action of the spin current.

Abstract: Exemplary embodiments of the present disclosure provide a spin valve and a spintronic device comprising the same. The spin valve may comprise two or more magnetic layers stacked in sequence, wherein the spin valve further comprises at least one pair of nonmagnetic semiconductor layers arranged between any two adjacent magnetic layers among the two or more magnetic layers, wherein a built-in electric field is formed between the at least one pair of nonmagnetic semiconductor layers.

Abstract: Provided are a semiconductor material based on metal nanowires and a porous nitride, and a preparation method thereof. The semiconductor material includes: a substrate; a buffer layer formed on the substrate; and a composite material layer formed on the buffer layer the composite material layer includes: a transverse porous nitride template layer; and a plurality of metal nanowires filled in pores of the transverse porous nitride template layer.

Abstract: A GaN-based VCSEL chip based on porous DBR and a manufacturing method of the same, wherein the chip includes: a substrate; a buffer layer formed on the substrate; a bottom porous DBR layer formed on the buffer layer; an n-type doped GaN layer formed on the bottom porous DBR layer, which is etched downward on its periphery to form a mesa; an active layer formed on the n-type doped GaN layer; an electron blocking layer formed on the active layer; a p-type doped GaN layer formed on the electron blocking layer; a current limiting layer formed on the p-type doped GaN layer with a current window formed at a center thereof, wherein the current limiting layer covers sidewalls of the active layer, the electron blocking layer and the convex portion of the n-type doped GaN layer; a transparent electrode formed on the p-type doped GaN layer; an n-electrode formed on the mesa of the n-type doped GaN layer; a p-electrode formed on the transparent electrode with a recess formed therein; and a dielectric DBR layer formed on

Abstract: Exemplary embodiments of the present disclosure provide a spin valve and a spintronic device comprising the same. The spin valves may comprise two or more magnetic layers stacked in sequence, wherein any two adjacent magnetic layers among the two or more magnetic layers have different coercive forces, and at least one of the any two adjacent magnetic layers is a van der Waals magnetic layer, wherein the van der Waals magnetic layer refers to a magnetic layer made of a van der Waals magnetic material.

Abstract: Exemplary embodiments of the present disclosure provide a spin valve and a spintronic device comprising the same. The spin valves may comprise two or more magnetic layers stacked in sequence, wherein any two adjacent magnetic layers among the two or more magnetic layers have different coercive forces, and at least one of the any two adjacent magnetic layers is a van der Waals magnetic layer, wherein the van der Waals magnetic layer refers to a magnetic layer made of a van der Waals magnetic material.

Abstract: Exemplary embodiments of the present disclosure provide a spin valve and a spintronic device comprising the same. The spin valve may comprise two or more magnetic layers stacked in sequence, wherein the spin valve further comprises at least one pair of nonmagnetic semiconductor layers arranged between any two adjacent magnetic layers among the two or more magnetic layers, wherein a built-in electric field is formed between the at least one pair of nonmagnetic semiconductor layers.

Abstract: A voltage controlled magnetic random memory unit, a memory, and a logic device thereof. The memory unit includes: a ferroelectric layer applied with a first positive or negative voltage to control a directional switching of magnetization; a spin-orbit coupling layer located above the ferroelectric layer and applied with a second voltage to produce a spin current in a direction perpendicular to the spin-orbit coupling layer; a first magnetic layer located above the spin-orbit coupling layer, wherein, the spin current induces a random up and down magnetic switching of the first magnetic layer. The spin current may induce a directional switching of the first magnetic layer in conjunction with the first voltage applied to the ferroelectric layer.

Abstract: An InGaN-based resonant cavity enhanced detector chip based on porous DBR, including: a substrate (10); a buffer layer (11) formed on the substrate (10); a bottom porous DBR layer (12) formed on the buffer layer (11); an n-type GaN layer (13) formed on the bottom porous DBR layer (12), wherein one side of the n-type GaN layer (13) is recessed downward to form a mesa (13?), and the other side of the n-type GaN layer (13) is protruded; an active region (14) formed on the n-type GaN layer (13); a p-type GaN layer (15) formed on the active region (14); a sidewall passivation layer (20) formed on an upper surface of the p-type GaN layer (15) and sidewalls of the protruded n-type GaN layer (13), the active region (14), and the p-type GaN layer (15), wherein the sidewall passivation layer (20) on the upper surface of the p-type GaN layer (15) has a window in a middle; a transparent conductive layer (16) formed on the sidewall passivation layer (20) and the p-type GaN layer (15) at the window; an n-type electrode (18

Abstract: A voltage controlled magnetic random memory unit, a memory, and a logic device thereof. The memory unit includes: a ferroelectric layer applied with a first positive or negative voltage to control a directional switching of magnetization; a spin-orbit coupling layer located above the ferroelectric layer and applied with a second voltage to produce a spin current in a direction perpendicular to the spin-orbit coupling layer; a first magnetic layer located above the spin-orbit coupling layer, wherein, the spin current induces a random up and down magnetic switching of the first magnetic layer. The spin current may induce a directional switching of the first magnetic layer in conjunction with the first voltage applied to the ferroelectric layer.

Abstract: A GaN-based VCSEL chip based on porous DBR and a manufacturing method of the same, wherein the chip includes: a substrate; a buffer layer formed on the substrate; a bottom porous DBR layer formed on the buffer layer; an n-type doped GaN layer formed on the bottom porous DBR layer, which is etched downward on its periphery to form a mesa; an active layer formed on the n-type doped GaN layer; an electron blocking layer formed on the active layer; a p-type doped GaN layer formed on the electron blocking layer; a current limiting layer formed on the p-type doped GaN layer with a current window formed at a center thereof, wherein the current limiting layer covers sidewalls of the active layer, the electron blocking layer and the convex portion of the n-type doped GaN layer; a transparent electrode formed on the p-type doped GaN layer; an n-electrode formed on the mesa of the n-type doped GaN layer; a p-electrode formed on the transparent electrode with a recess formed therein; and a dielectric DBR layer formed on

Abstract: An InGaN-based resonant cavity enhanced detector chip based on porous DBR, including: a substrate (10); a buffer layer (11) formed on the substrate (10); a bottom porous DBR layer (12) formed on the buffer layer (11); an n-type GaN layer (13) formed on the bottom porous DBR layer (12), wherein one side of the n-type GaN layer (13) is recessed downward to form a mesa (13?), and the other side of the n-type GaN layer (13) is protruded; an active region (14) formed on the n-type GaN layer (13); a p-type GaN layer (15) formed on the active region (14); a sidewall passivation layer (20) formed on an upper surface of the p-type GaN layer (15) and sidewalls of the protruded n-type GaN layer (13), the active region (14), and the p-type GaN layer (15), wherein the sidewall passivation layer (20) on the upper surface of the p-type GaN layer (15) has a window in a middle; a transparent conductive layer (16) formed on the sidewall passivation layer (20) and the p-type GaN layer (15) at the window; an n-type electrode (18