Patents by Inventor Kaiyu Chen

Kaiyu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop
    Patent number: 7585705
    Abstract: A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: a) Fabricate numerous trench MOSFETs on a wafer. b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer. c) Add numerous ESD protection modules atop the Si3N4 isolation layer. d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules. In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: September 8, 2009
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Mengyu Pan, Zengyi He, Kaiyu Chen
  • Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop
    Publication number: 20090140333
    Abstract: A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: a) Fabricate numerous trench MOSFETs on a wafer. b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer. c) Add numerous ESD protection modules atop the Si3N4 isolation layer. d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules. In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 4, 2009
    Inventors: Mengyu Pan, Zengyi He, Kaiyu Chen