Patents by Inventor Kaiyu Ren

Kaiyu Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Functional failure analysis techniques for programmable integrated circuits
    Patent number: 7685485
    Abstract: Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: March 23, 2010
    Assignee: Altera Corporation
    Inventors: Binh Vo, Wan-Pin Hung, David Huang, Peter Boyle, Qi Richard Chen, Kaiyu Ren, Adam J. Wright, John DiCosola, Laiq Chughtai, Seng Yew Lim
  • Bit error rate tester implemented in a programmable logic device
    Patent number: 7194666
    Abstract: The present invention provides a bit error rate tester implemented in a programmable logic device. Any or all of the components of the bit error rate tester may be implemented through software by programming the programmable logic circuitry of the programmable logic device to implement the components of the bit error rate tester. The bit error tester may determine the bit error rate of any suitable interface either within the programmable logic device or external to the programmable logic device. In order to allow a user to interact with the bit error rate tester, user equipment, such as a personal computer, may be coupled to the bit error rate tester.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: March 20, 2007
    Assignee: Altera Corporation
    Inventors: San Wong, Kaiyu Ren
  • Functional failure analysis techniques for programmable integrated circuits
    Publication number: 20050022085
    Abstract: Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.
    Type: Application
    Filed: October 30, 2003
    Publication date: January 27, 2005
    Applicant: Altera Corporation
    Inventors: Binh Vo, Wan-Pin Hung, David Huang, Peter Boyle, Qi Chen, Kaiyu Ren, Adam Wright, John DiCosola, Laiq Chughtai, Seng Lim