Abstract: A switch system (20) switches at least sixty-four asynchronous transfer mode (ATM) input data streams (22) into at least sixty-four ATM output data streams (24). The switch system (20) includes a backplane assembly (38) having integral data transmission lines, integral clock transmission lines, and discrete slots (36). A single stage space switch circuit card (26), a clock circuit card (28), and input circuit cards (30) are connected to separate slots (36) in the backplane assembly (38). The integral data transmission lines are coupled between the input circuit cards (30) and the switch circuit card (26) and the integral clock transmission lines are coupled between the clock circuit card (28) and the input circuit cards (30). Data path lengths for the integral data transmission lines differ in the backplane assembly (38), and clock path lengths for the clock transmission lines differ in the backplane assembly.

Abstract: A high speed packet switch (100) is provided which uses a fabric size of 128.times.128 and operates at a 2.5 Gbps rate. Parallel data transport techniques are used to obtain the 2.5 Gbps data rate while operating internal switches (160) at slower rates. The packet switch fabric is fabricated on a single ASIC using high speed CMOS.