Patents by Inventor Kajetan Nuernberger

Kajetan Nuernberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240184253
    Abstract: According to various embodiments, a training arrangement for training a machine learning model for state determination in closed-loop control is described, comprising a microcontroller and a data processing system external to the microcontroller. The microcontroller comprises a trace system configured to capture operational information state information determined by a machine learning model of the microcontroller and to transmit them to the data processing system which is configured to compare the determined state information with ground truth sensor information, to determine whether an update for the machine learning model is required depending on the comparison and, if it has determined that an update for the machine learning model is required, to determine an update for the machine learning model and transmit the update to the microcontroller. The microcontroller is configured to update the machine learning model in response to the reception of an update from the data processing system.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 6, 2024
    Inventor: Kajetan NUERNBERGER
  • Publication number: 20230267094
    Abstract: In various examples, a system on a chip is provided that is configured to be operated in a debug mode. The system on a chip includes a plurality of processor cores including a plurality of virtual machines and a further processor core, configured to, in the debug mode, initially execute first debug instructions after the system on a chip has started operating. The first debug instructions are configured to cause the further processor core to make a debug setting that, after the first debug instructions are executed, prevents a processor core executing second debug instructions from accessing at least one of the virtual machines and allows the processor core executing the second debug instructions to access at least one other of the virtual machines.
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Inventors: Albrecht Mayer, Patrik Eder, Kajetan Nuernberger