Abstract: The semiconductor device includes a semiconductor wafer which is partitioned into chip regions by scribe line area. A device pattern is formed in the device forming region included in the chip region. A monitor pattern is formed from the same material as that of the device patterns in the chip region simultaneously with the device pattern. An interlayer insulating film is formed in the chip region so as to cover the device pattern and the monitor pattern. The monitor pattern is used to measure the thickness of the interlayer insulating film.

Abstract: In a semiconductor device having a bipolar transistor and a MOS transistor on a same semiconductor substrate, a gate electrode of MOS transistor is formed of a first gate electrode layer on a gate oxide film and a second gate electrode layer formed on the first gate electrode layer. Nitrogen is introduced into the first gate electrode layer, and is aggregated around the interface with the gate oxide film. Arsenic is implanted into a second gate electrode layer, and diffused into the second gate electrode layer. An emitter electrode of a bipolar transistor is formed of the same layer with the second gate electrode layer, but nitrogen is not introduced.

Abstract: The semiconductor device includes a semiconductor wafer which is partitioned into chip regions by scribe line area. A device pattern is formed in the device forming region included in the chip region. A monitor pattern is formed from the same material as that of the device patterns in the chip region simultaneously with the device pattern. An interlayer insulating film is formed in the chip region so as to cover the device pattern and the monitor pattern. The monitor pattern is used to measure the thickness of the interlayer insulating film.

Abstract: The semiconductor device includes a semiconductor wafer which is partitioned into chip regions by scribe line area. A device pattern is formed in the device forming region included in the chip region. A monitor pattern is formed from the same material as that of the device patterns in the chip region simultaneously with the device pattern. An interlayer insulating film is formed in the chip region so as to cover the device pattern and the monitor pattern. The monitor pattern is used to measure the thickness of the interlayer insulating film.

Abstract: A semiconductor device includes: an insulation layer; a fuse layer extending on the insulation layer in one direction and disconnected through light radiation to control a redundant circuit; a pseudo fuse layer on the insulation layer along at least one side of the fuse layer; another insulation layer covering the fuse layer and the pseudo fuse layer; and a protection film formed on another insulation layer and having an opening in a region opposite to the fuse layer. Fuse layers having a spacing of less than 4 &mgr;m or 4.5 to 5.5 &mgr;m. Such a structure allows a semiconductor device with a fuse layer capable of being disconnected reliably and providing a smaller blow trace.

Abstract: A semiconductor device with a reduced insulating capacitance between an emitter electrode and a base layer, and a manufacturing method thereof are disclosed. In the semiconductor device, at least first and second insulating layers are interposed between the emitter electrode and the base layer. Preferably, the first insulating layer, a semiconductor layer having insulation characteristics, and the second insulating layer are interposed between the emitter electrode and the base layer.

Abstract: A method of manufacturing a semiconductor device can suppress an etching damage to a bipolar transistor part and a CMOS transistor part while simplifying a manufacturing process. According to this manufacturing method, an external base leader electrode layer which will form an external base leader electrode is used as an etching protection film for forming a CMOS transistor, and a layered film including a polycrystalline silicon film which will ultimately form a gate electrode is used as an etching protection film during formation of a bipolar transistor. Thereby, a step of forming the etching protection film can be utilized also as a step of forming the external base electrode and the gate electrode. Consequently, the etching damages to the bipolar transistor part and the CMOS transistor part are suppressed while simplifying the manufacturing process.

Abstract: A semiconductor device with a reduced insulating capacitance between an emitter electrode and a base layer, and a manufacturing method thereof are disclosed. In the semiconductor device, at least first and second insulating layers are interposed between the emitter electrode and the base layer. Preferably, the first insulating layer, a semiconductor layer having insulation characteristics, and the second insulating layer are interposed between the emitter electrode and the base layer.

Abstract: A p.sup.- semiconductor substrate has a surface which is high in a memory cell region and low in a peripheral circuit region. An n.sup.+ buried semiconductor layer of uniform thickness is formed on the substrate. An n.sup.- epitaxial layer formed on the buried semiconductor layer is thin in the memory cell region and thick in the peripheral circuit region, so that the surface of the epitaxial layer can be flat. A concave or convex step is formed on the surface of the epitaxial layer in a boundary portion between the memory cell region and the peripheral circuit region in order to use it as an alignment mark in a later processing step.

Abstract: A p.sup.- semiconductor substrate has a surface which is high in a memory cell region and low in a peripheral circuit region. An n.sup.+ buried semiconductor layer of uniform thickness is formed on the substrate. An n.sup.- epitaxial layer formed on the buried semiconductor layer is thin in the memory cell region and thick in the peripheral circuit region, so that the surface of the epitaxial layer can be flat. A concave or convex step is formed on the surface of the epitaxial layer in a boundary portion between the memory cell region and the peripheral circuit region in order to use it as an alignment mark in a later processing step.

Abstract: A bipolar RAM comprising a plurality of memory cells formed of cross-coupled bipolar transistors and a peripheral bipolar circuit formed of bipolar transistor, provided with an epitaxial layer which is to be the collector region of the bipolar transistor in the memory cell portion which is thinner and has higher impurity density than the epitaxial layer which is to be the collector region of a bipolar transistor in the peripheral circuit.

Abstract: In a method of manufacturing a semiconductor device according to the present invention, regions of first conductivity type buried layers formed on a first conductivity type substrate are retracted with respect to regions of second conductivity type buried layers. Thus, in formation of second conductivity type epitaxial layer, first conductivity type impurity contained in the first conductivity type buried layers is prevented from floating diffusion up to element regions of the second conductivity type epitaxial layers. At the same time, the semiconductor device can be implemented with high density of integration.

Abstract: In a method of manufacturing a semiconductor device according to the present invention, regions of first conductivity type buried layers formed on a first conductivity type substrate are retracted with respect to regions of second conductivity type buried layers. Thus, in formation of second conductivity type epitaxial layer, first conductivity type impurity contained in the first conductivity type buried layers is prevented from floating diffusion up to element regions of the second conductivity type epitaxial layers. At the same time, the semiconductor device can be implemented with high density of integration.

Abstract: According to the present invention, a method for forming a metal silicide electrode in contact with a doped region of a silicon substrate through a contact hole which is opened through an insulator film over said substrate, comprises the steps of: covering not only the contact hole area but also the insulator film with a metal film; injecting silicon ions into a predetermined area of the metal film covering the insulator portion adjacent the contact hole area; forming a continuous metal siliside film by annealing only on both the hole area and the ion-injected area; removing the metal film to leave the metal silicide film as an electrode which extends laterally to cover the hole area and the adjacent insulator portion. According to another aspect of the present invention, silicon ions are implanted into the area of the indulating film adjacent the contact hole area prior to a conformal deposition of metal. An annealing hep is carried out to form silicide.

Abstract: In a method for fabricating a bipolar transistor in accordance with the present invention, a base electrode (9a) of metal silicide is formed being separated from an emitter region (7) only by the thickness of a double-layered insulator film (109, 203).