Abstract: Embodiments herein include an optical system that passively aligns a fiber array connector (FAC) to a waveguide in a photonic chip. A substrate of the FAC is machined or etched to include multiple grooves along a common axis or plane to hold optical waveguides, or more specifically, the fibers of the optical cables in the FAC. To align the fibers to the photonic chip, one of the fibers is disposed in an alignment trench which has a width that is substantially the same as the diameter of the fiber. When the fiber registers with the alignment trench, the fiber is aligned with a waveguide disposed at the end of the trench. Because the pitch between the fibers can be precisely controlled, aligning one of the fibers using the alignment trench results in the other fibers becoming passively aligned to respective waveguides in the photonic chip.

Abstract: Embodiments herein include an optical system that passively aligns a fiber array connector (FAC) to a waveguide in a photonic chip. A substrate of the FAC is machined or etched to include multiple grooves along a common axis or plane to hold optical waveguides, or more specifically, the fibers of the optical cables in the FAC. To align the fibers to the photonic chip, one of the fibers is disposed in an alignment trench which has a width that is substantially the same as the diameter of the fiber. When the fiber registers with the alignment trench, the fiber is aligned with a waveguide disposed at the end of the trench. Because the pitch between the fibers can be precisely controlled, aligning one of the fibers using the alignment trench results in the other fibers becoming passively aligned to respective waveguides in the photonic chip.

Abstract: A multi-channel clock recovery circuit is provided that generates pairs of recovered half-speed clocks. Each pair of half-speed clocks has a relative phase relationship of 180° and are capable of registering input data of a data channel at the eye of the input data. The multi-phase clock recovery circuit includes a voltage controlled oscillator outputting a plurality of half-speed reference clocks. Each of a plurality of clock recovery circuits include a phase locked loop having a phase multiplexor, the phase multiplexor receiving the plurality of half-speed reference clocks and selectively outputting four recovered half-speed clocks each having a half-speed frequency relative to the input data. The four recovered clocks are used as a feedback reference clocks in the phase locked loop and two of the four recovered half-speed clocks are used to synchronize input data.

Abstract: A multi-channel clock recovery circuit is provided that generates pairs of recovered half-speed clocks. Each pair of half-speed clocks has a relative phase relationship of 180° and are capable of registering input data of a data channel at the eye of the input data. The multi-phase clock recovery circuit includes a voltage controlled oscillator outputting a plurality of half-speed reference clocks. Each of a plurality of clock recovery circuits include a phase locked loop having a phase multiplexor, the phase multiplexor receiving the plurality of half-speed reference clocks and selectively outputting four recovered half-speed clocks each having a half-speed frequency relative to the input data. The four recovered clocks are used as a feedback reference clocks in the phase locked loop and two of the four recovered half-speed clocks are used to synchronize input data.