Abstract: An exemplary multi-threaded memory management system comprises a memory management unit (MMU) configured with a plurality of physical address (PA) output ports individually dedicated to a respective plurality of threads, wherein the MMU is configured to adjust scheduling of the plurality of threads based on the status of an item requested from a cache. The MMU may be configured to translate a virtual address (VA) input from an individual thread to a PA output on the respective PA output port. The cache may be a translation look-aside buffer. The item requested from the cache may be in transient status when a response is expected or valid status when the response is received. The MMU may signal a thread scheduler to run a thread when a requested item's status becomes valid, permitting stalling individual threads without blocking other threads that continue running using the PA output port dedicated to each thread.

Abstract: An exemplary multi-threaded memory management system comprises a memory management unit (MMU) configured with a plurality of physical address (PA) output ports individually dedicated to a respective plurality of threads, wherein the MMU is configured to adjust scheduling of the plurality of threads based on the status of an item requested from a cache. The MMU may be configured to translate a virtual address (VA) input from an individual thread to a PA output on the respective PA output port. The cache may be a translation look-aside buffer. The item requested from the cache may be in transient status when a response is expected or valid status when the response is received. The MMU may signal a thread scheduler to run a thread when a requested item's status becomes valid, permitting stalling individual threads without blocking other threads that continue running using the PA output port dedicated to each thread.