Patents by Inventor Kalipatnam Rao
Kalipatnam Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110215299Abstract: A semiconductor device may include a substrate and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel including a plurality of stacked groups of layers, a source and a drain adjacent the superlattice channel, and a gate adjacent the superlattice channel. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first dopant may be in at least one region adjacent at least one of the source and drain, and a second dopant may also be in the at least one region. The second dopant may be different than the first dopant and reduce diffusion thereof.Type: ApplicationFiled: March 8, 2011Publication date: September 8, 2011Applicant: MEARS Technologies, Inc.Inventor: KALIPATNAM RAO
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Publication number: 20070063186Abstract: A method for making a semiconductor device may include forming a stress layer on a back surface of a semiconductor substrate and forming a strained superlattice layer adjacent a front surface of the semiconductor substrate. More particularly, the stress layer may include a material different than the semiconductor substrate. Also, the strained superlattice may include a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: September 25, 2006Publication date: March 22, 2007Applicant: RJ Mears, LLCInventor: Kalipatnam Rao
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Semiconductor device including a front side strained superlattice layer and a back side stress layer
Publication number: 20070063185Abstract: A semiconductor device may include a semiconductor substrate having front and back surfaces, a strained superlattice layer adjacent the front surface of the semiconductor substrate and comprising a plurality of stacked groups of layers, and a stress layer on the back surface of the substrate and comprising a material different than the semiconductor substrate. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: September 25, 2006Publication date: March 22, 2007Applicant: RJ Mears, LLCInventor: Kalipatnam Rao -
Publication number: 20060292818Abstract: A method for making a semiconductor device may include forming an insulating layer on a substrate, and forming a semiconductor layer on the insulating layer on a side thereof opposite the substrate. The method may further include forming a superlattice on the semiconductor layer on a side thereof opposite the insulating layer. The superlattice may include a plurality of stacked groups of layers, with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. Moreover, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: June 30, 2006Publication date: December 28, 2006Applicant: RJ Mears, LLCInventor: Kalipatnam Rao
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Publication number: 20060289049Abstract: A semiconductor device may include a substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer on a side thereof opposite the substrate. The semiconductor device may further include a superlattice on the semiconductor layer on a side thereof opposite the insulating layer. The superlattice may include a plurality of stacked groups of layers, with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: June 30, 2006Publication date: December 28, 2006Applicant: RJ Mears, LLCInventor: Kalipatnam Rao
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Publication number: 20060292765Abstract: A method for making a semiconductor device may include forming at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite sides of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups of layers Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: June 28, 2006Publication date: December 28, 2006Applicant: RJ Mears, LLCInventors: Richard Blanchard, Kalipatnam Rao, Scott Kreps
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Publication number: 20060292889Abstract: A semiconductor device may include at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: June 28, 2006Publication date: December 28, 2006Applicant: RJ Mears, LLCInventors: Richard Blanchard, Kalipatnam Rao, Scott Kreps
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Publication number: 20060270169Abstract: A method for making a semiconductor device may include forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate. Further, a plurality of layers may be deposited over the substrate to define respective superlattices over the substrate between adjacent STI regions and to define respective non-monocrystalline regions over the STI regions. The method may further include selectively removing at least portions of the non-monocrystalline regions using at least one active area (AA) mask.Type: ApplicationFiled: June 20, 2006Publication date: November 30, 2006Applicant: RJ Mears, LLCInventor: Kalipatnam Rao
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Publication number: 20060267130Abstract: A semiconductor device may include a semiconductor substrate and a plurality of shallow trench isolation (STI) regions in the substrate. More particularly, at least some of the STI regions may include divots therein. The semiconductor device may further include a respective superlattice between adjacent STI regions, and respective non-monocrystalline stringers in the divots.Type: ApplicationFiled: June 20, 2006Publication date: November 30, 2006Applicant: RJ Mears, LLCInventor: Kalipatnam Rao
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Publication number: 20060263980Abstract: A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one non-volatile memory cell. Spaced apart source and drain regions may be formed, and a superlattice channel may be formed between the source and drain regions. The superlattice channel may include a plurality of stacked groups of layers on the substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be formed adjacent the superlattice channel, and a control gate may be formed adjacent the floating gate.Type: ApplicationFiled: May 5, 2006Publication date: November 23, 2006Applicant: RJ Mears, LLC, State of Incorporation: DelawareInventors: Scott Kreps, Kalipatnam Rao
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Publication number: 20060261327Abstract: A semiconductor device may include a substrate, an insulating layer adjacent the substrate, and a semiconductor layer adjacent a face of the insulating layer opposite the substrate. The device may further include source and drain regions on the semiconductor layer, a superlattice adjacent the semiconductor layer and extending between the source and drain regions to define a channel, and a gate overlying the superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: May 5, 2006Publication date: November 23, 2006Applicant: RJ Mears, LLCInventors: Scott Kreps, Kalipatnam Rao
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Publication number: 20060243963Abstract: A semiconductor device may include a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, which may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be adjacent the superlattice channel, and a control gate may be adjacent the second gate insulating layer.Type: ApplicationFiled: May 5, 2006Publication date: November 2, 2006Applicant: RJ Mears, LLCInventors: Scott Kreps, Kalipatnam Rao
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Publication number: 20060243964Abstract: A method for making a semiconductor device may include forming an insulating layer adjacent a substrate, forming a superlattice adjacent a semiconductor layer, and positioning the semiconductor layer adjacent a face of the insulating layer opposite the substrate. The method may further include forming a gate overlying the superlattice, and forming source and drain regions on the semiconductor layer so that the superlattice extends therebetween to define a channel. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: May 5, 2006Publication date: November 2, 2006Applicant: RJ Mears, LLCInventors: Scott Kreps, Kalipatnam Rao
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Publication number: 20060019454Abstract: A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a high-K dielectric layer on the electrode layer, and forming an electrode layer on the high-K dielectric layer and opposite the superlattice.Type: ApplicationFiled: May 25, 2005Publication date: January 26, 2006Applicant: RJ Mears, LLCInventors: Robert Mears, Marek Hytha, Scott Kreps, Robert Stephenson, Jean Augustin Yiptong, Ilija Dukovski, Kalipatnam Rao, Samed Halilov, Xiangyang Huang
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Publication number: 20060011905Abstract: A semiconductor device may include a semiconductor substrate and at least one active device adjacent the semiconductor substrate. The at least one active device may include an electrode layer, a high-K dielectric layer underlying the electrode layer and in contact therewith, and a superlattice underlying the high-K dielectric layer opposite the electrode layer and in contact with the high-K dielectric layer. The superlattice may include a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: May 25, 2005Publication date: January 19, 2006Applicant: RJ Mears, LLCInventors: Robert Mears, Marek Hytha, Scott Kreps, Robert Stephenson, Jean Augustin Chan yiptong, Ilija Dukovski, Kalipatnam Rao, Samed Halilov, Xiangyang Huang