Abstract: An apparatus includes a decoder to receive a compressed bit stream that is based on a coding standard. The decoder includes a hardware accelerator to decode a part of the compressed bit stream that is based on an operation that is common across multiple coding standards that includes the coding standard. The decoder also includes a programmable element to decode a part of the compressed bit stream that is based on an operation that is specific to the coding standard.

Abstract: According to some embodiments, context information is accessed for a current image block being processed. The context information may be, for example, associated with a block neighboring the current block, and the accessing may be performed in accordance with an address. At least one of a plurality of modular indexes may then be adjusted, and a next address may be determined in accordance with the plurality of modular indexes.

Abstract: In one embodiment, a method and apparatus for filtering input pixel data is configurable to perform a one-dimensional or two-dimensional filtering process. Further, in one embodiment, the two-dimensional filter can be configured to perform a separable or non-separable filter. The type of filter can be configured, along with the size of the filter and other parameters. During operation, a stage I filtering operation performs a portion of the filter, and temporarily stores the result in a storage element. If the filter is a one-dimensional filter, then the results are sent to be post-processed. If the filter is a two-dimensional filter, then a stage II filtering process is performed or the intermediate results are added together, based on whether the filter is separable or non-separable. These results are then post-processed.

Abstract: A processing block is equipped with a storage to facilitate storage and maintenance of a thread switching structure to provide multi-threading support in a light-weight manner. In various embodiments, the structure includes a current thread identifier, and a thread array of thread entries describing the threads to be executed interleavingly. Further, in various embodiments, the processing block includes an execution sub-block and a thread management sub-block equipped to support at least a create thread, a thread execution termination, and a thread execution switching instruction.

Abstract: A device including a variable length coding unit that includes an input unit connected to a stream switching unit, and an output unit connected to the stream switching unit. The input unit to encode at least two input streams simultaneously. The output unit to transmit output streams to an output interface connected to the output unit.

Abstract: According to some embodiments, it is determined if a register is ready to exchange data with a processing element.

Abstract: An address generator is provided with an input to receive a base address for an array of storage locations, an offset generator to generate a number of offsets, and a combiner coupled to the input and the offset generator to combine the base address with the offsets to generate a number of access addresses for accessing the array of storage locations in accordance with a deterministic access pattern having at least one non-sequential access. In various embodiments, the address generator is included in each of a number of signal processing units, which in turn are included in a digital media processor.

Abstract: Embodiments relate to converting or compressing symbols or run, level pair of an input digital video or image data stream to variable length code (VLC) by looking the symbols or run, level pairs up in a table including a binary code, a length code, and a flip code and constructing the VLC therefrom. For instance, the binary code may identify a first non-zero portion of the VLC, the length may identify the length of the VLC, and the flip code may identify whether or not the first portion and a number of 0's appended to the first portion to form a VLC having the length given by the length code, must be inverted to create the VLC. Also, the table may include entries grouped according to symbol or run, level pair values, and an address offset determined by the symbol or run, level pair or the input may be used to access the binary, length, and flip code from the appropriate group.

Abstract: An apparatus for gathering queue performance data includes an event conditioning logic unit that receives a queue enter signal, a queue exit signal, and a queue not empty signal from a queue. The apparatus also includes a counter that may be both incremented and decremented. The event conditioning logic unit may be programmed to increment the counter upon occurrences of a predetermined combination of the queue signals. The event conditioning logic unit may also be programmed to decrement the counter upon occurrences of an additional predetermined combination of the queue signals.

Abstract: According to some embodiments, it is determined if a register is ready to exchange data with a processing element.

Abstract: A method for employing an associative memory to implement a switch is disclosed. The method comprises the step of receiving data in a first time slot. The method also comprises the step of examining the associative memory to determine if the data should be stored. Additionally, the method comprises the step of storing the data in a memory location and transmitting the data in a second time slot.

Abstract: A method for employing an associative memory to implement a message passing switch. The method comprising the step of receiving data in a time slot. The method also comprising the step of examining an interrupt register to determine if the data is a message. Additionally, the method comprises the step of storing the data in a memory location and transferring the data to an external device.

Abstract: An apparatus for gathering queue performance data includes an event conditioning logic unit that receives a queue enter signal, a queue exit signal, and a queue not empty signal from a queue. The apparatus also includes a counter that may be both incremented and decremented. The event conditioning logic unit may be programmed to increment the counter upon occurrences of a predetermined combination of the queue signals. The event conditioning logic unit may also be programmed to decrement the counter upon occurrences of an additional predetermined combination of the queue signals.

Abstract: A method for employing an associative memory to implement a message passing switch. The method comprising the step of receiving data in a time slot. The method also comprising the step of examining an interrupt register to determine if the data is a message. Additionally, the method comprises the step of storing the data in a memory location and transferring the data to an external device.