Abstract: A method, device and a system of determining a concentration of one or more analytes in a sample is disclosed. In one aspect of the invention, the method includes introducing the sample through a channel. The method further includes illuminating the sample with light having varying wavelengths. Additionally, the method includes obtaining an image of the illuminated sample at each of the wavelengths. Furthermore, the method includes analyzing the image to determine the concentration of the one or more analytes.

Abstract: The invention relates to a ptychographic imaging system that includes a plurality of light sources adapted to emit light onto a sample location, wherein the light sources are arranged in a predefined pattern; the system also includes a controller adapted to control operation of the plurality of light sources; wherein at least one of a) the predefined pattern of the light sources and b) the operation of the plurality of light sources is adapted to compensate for geometric effects due to an arrangement of the light sources relative to the sample location.

Abstract: An adaptive hardware trace circuit is presented. The adaptive hardware trace circuit may include one or more trace circuits, a trace port funnel circuit, a trace FIFO buffer, and an adaptation logic circuit. Each trace circuit may be coupled to a processor core and configured to monitor and encode trace data generated by a processor core. The trace buffer may be configured to store the trace data generated by the processor cores. The adaptation circuit may be configured to receive, from a user, one or more buffer capacity thresholds and a priority level assigned to each trace. The adaptation circuit may map ranges of trace buffer capacities to corresponding sets of actions. The adaptation circuit may detect a buffer capacity to determine a set of one or more actions associated with the buffer capacity and execute the set of one or more actions.

Abstract: A method and system for determining a concentration of one or more analytes in whole blood is provided. In one aspect of the invention, the system includes a channel configured to carry whole blood. The system further includes a light source configured to emit light on the channel. Additionally, the system includes an actuation module associable with the channel, wherein the actuation module is configured to generate a cell-free plasma layer in the channel. Furthermore, the system includes an optical module associable with the channel.

Abstract: A method and a device for determining a concentration of one or more analytes in a whole blood sample is disclosed. In one aspect of the invention, the method includes introducing the sample in a channel. The method further includes generating a cell-free plasma region in the channel, wherein the cell-free plasma region is generated in the channel based on rouleaux effect. The method further includes illuminating the sample with light having varying wavelengths. Additionally, the method includes obtaining an image of the illuminated sample at each of the wavelengths. Furthermore, the method includes analyzing the image to determine the concentration of the one or more analytes.

Abstract: The invention relates to a ptychographic imaging system, comprising a plurality of light sources adapted to emit light onto a sample location, wherein said light sources are arranged in a predefined pattern; and a controller adapted to control operation of said plurality of light sources; wherein at least one of a) said predefined pattern of the light sources and b) said control operation of the plurality of light sources is adapted to compensate for geometric effects due to an arrangement of the light sources relative to the sample location.

Abstract: A method and system for determining a concentration of one or more analytes in whole blood is provided. In one aspect of the invention, the system includes a channel configured to carry whole blood. The system further includes a light source configured to emit light on the channel. Additionally, the system includes an actuation module associable with the channel, wherein the actuation module is configured to generate a cell-free plasma layer in the channel. Furthermore, the system includes an optical module associable with the channel.

Abstract: A method, device and a system of determining a concentration of one or more analytes in a sample is disclosed. In one aspect of the invention, the method includes introducing the sample through a channel The method further includes illuminating the sample with light having varying wavelengths. Additionally, the method includes obtaining an image of the illuminated sample at each of the wavelength. Furthermore, the method includes analyzing the image to determine the concentration of the one or more analytes.

Abstract: A method and a device for determining a concentration of one or more analytes in a whole blood sample is disclosed. In one aspect of the invention, the method includes introducing the sample in a channel. The method further includes generating a cell-free plasma region in the channel, wherein the cell-free plasma region is generated in the channel based on rouleaux effect. The method further includes illuminating the sample with light having varying wavelengths. Additionally, the method includes obtaining an image of the illuminated sample at each of the wavelengths. Furthermore, the method includes analyzing the image to determine the concentration of the one or more analytes.

Abstract: An apparatus is described comprising: logic circuitry to take an absolute difference between: 1) less than all of the bits of an uncompressed video data value from a reference macro block and 2) less than all of the bits of an uncompressed video data value from a macro block worth of data within a search window. The apparatus further includes a register to store the reference macro block. The register is coupled to the logic circuitry. The apparatus further include a random access memory to store the search window. The random access memory is coupled to the logic circuitry.

Abstract: Values are calculated which control the manner in which a display streamer directs the movement of display data. The values are stored in the display streamer.

Abstract: Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.

Abstract: A method, apparatus,and system for performing motion estimation using a logarithmic search are described. One or more image signal processing engines including a plurality of processing elements are employed. The one or more image signal processing engines are mutually coupled by a register file switch, and the one or more image signal processing engines perform a block matching calculation that includes a sum of absolute differences. The plurality of processing elements is further mutually coupled such that, during the block matching calculation, parallel processing and pixel data sharing of reference block pixel locations is employed by the plurality of processing elements.

Abstract: In some embodiments, an apparatus comprises a hardware accelerator to execute one or more process operations on one or more pixels of a macroblock of a video frame that is based on a video standard. The apparatus also comprises a programmable element to process a configuration header of the macroblock. The programmable element configures one or more parameters of the one or more process operations of the hardware accelerator for the video standard based on the configuration header.

Abstract: Various embodiments of the invention relate to communicating data between a number of processing elements (PEs) of a signal processor, using a plurality of communication registers (CCRs). For instance, a plurality of the CCRs can be shared by and mapped to the address space of each PE, where each CCR couples a first of the PEs to every other one of the PEs. Moreover, each CCR can include a data payload field and a data valid field to indicate a target PE to read the data in the data payload field. Thus, data can be written to a selected CCR by a PE and stored in the selected CCR to be read by at least one target PE.

Abstract: According to some embodiments, a first filter receives input pixel information and provides a first output. A buffer stores the first output, and a second filter receives information from the buffer and provides output pixel information. Moreover, at least one of the first or second filters are configurable to support motion compensation for a plurality of video compression standards.

Abstract: According to some embodiments, context information is accessed for a current image block being processed. The context information may be, for example, associated with a block neighboring the current block, and the accessing may be performed in accordance with an address. At least one of a plurality of modular indexes may then be adjusted, and a next address may be determined in accordance with the plurality of modular indexes.

Abstract: An embodiment includes an apparatus that includes a first data processor component to output data in a first data organization. The apparatus also includes a data storage logic to receive the data output from the first data processor component. The data storage logic is to rearrange the data into a second data organization prior to storage of the data into a data storage. The second data organization is a native format of a second data processor component to subsequently process the data.

Abstract: An embodiment includes an apparatus that includes a decoder to receive a compressed bit stream that is based on a coding standard. The decoder includes a hardware accelerator to decode a part of the compressed bit stream that is based on an operation that is common across multiple coding standards that includes the coding standard. The decoder also includes a programmable element to decode a part of the compressed bit stream that is based on an operation that is specific to the coding standard.

Abstract: A system is described for processing data through single instruction multiple data (SIMD) operations. The system is coupled to receive a first operand and second operand, each of the operands having a length of N*M-bits. In one embodiment, N is an integer equal to or greater than two and M is an integer equal to or greater than two. The first operand is combined with first N-extra bits and are stored in a first (N*M)+N-bit register. The second operand is combined with a second N-extra bits and stored in a second (N*M)+N-bit register. The system logically combines values in the first register and the second register to obtain a result data having a length of N*M-bits. Other embodiments are described and claimed.