Abstract: The invention may relate to a digital frequency adjuster for adjusting a first frequency of a first signal. The digital frequency adjuster may comprise a first digital delay line and a first control circuit. The first digital delay line may comprise a plurality of taps. The first digital delay line may be configured to (i) receive the first signal and (ii) generate a second signal. The first control circuit may be configured to control dynamic assertion of respective ones of the taps at a rate such that the second signal has a second frequency different from the first frequency of the first signal.

Abstract: An apparatus for receiving and processing an electrical signal in the form of a pulse train comprising a plurality of pulses. The apparatus generally comprises a processor, a memory and a timer. The timer may be configured to generate a respective value representative of the positions of each leading and trailing edge of each pulse in the pulse train. The memory may be configured to receive the value and write the value. The timer may be configured to generate an interrupt signal following receipt of the trailing edge of the last pulse in the pulse train and apply the interrupt signal to the processor. The processor may read the values stored in the memory for decoding the pulse train in response to said interrupt signal.

Abstract: A method of performing data shifts in a data processing system between a source and a plurality of destinations using a direct memory accessing scheme, comprising the steps of: (A) reading a data block from the source destinations; (B) writing the data block to a first of the plurality of destinations; and (C) writing the data block to a second of the plurality of destinations. Addresses of the first and second destinations are previously stored.

Abstract: The invention may relate to a digital frequency adjuster for adjusting a first frequency of a first signal. The digital frequency adjuster may comprise a first digital delay line and a first control circuit. The first digital delay line may comprise a plurality of taps. The first digital delay line may be configured to (i) receive the first signal and (ii) generate a second signal. The first control circuit may be configured to control dynamic assertion of respective ones of the taps at a rate such that the second signal has a second frequency different from the first frequency of the first signal.

Abstract: A method of performing data shifts in a data processing system between a source and a plurality of destinations using a direct memory accessing scheme, comprising the steps of: (A) reading a data block from the source destinations; (B) writing the data block to a first of the plurality of destinations; and (C) writing the data block to a second of the plurality of destinations. Addresses of the first and second destinations are previously stored.

Abstract: An apparatus for receiving and processing an electrical signal in the form of a pulse train comprising a plurality of pulses. The apparatus generally comprises a processor, a memory and a timer. The timer may be configured to generate a respective value representative of the positions of each leading and trailing edge of each pulse in the pulse train. The memory may be configured to receive the value and write the value. The timer may be configured to generate an interrupt signal following receipt of the trailing edge of the last pulse in the pulse train and apply the interrupt signal to the processor. The processor may read the values stored in the memory for decoding the pulse train in response to said interrupt signal.