Patents by Inventor Kalyan C. Kavalipurapu
Kalyan C. Kavalipurapu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11322209Abstract: A memory device includes a memory array comprising a plurality of planes, a plurality of voltage generation systems, and a controller. Each voltage generation system is electrically coupled to a corresponding plane. The controller is configured to turn on and warm up each voltage generation system of the plurality of voltage generation systems in response to a first command to access any plane of the plurality of planes and turn off and slowly discharge each voltage generation system of the plurality of voltage generation systems into an idle state in response to no commands being processed. In response to receiving a subsequent command to access any plane of the plurality of planes prior to the voltage generation systems reaching the idle state, a warm up period of the plurality of voltage generation systems is reduced.Type: GrantFiled: May 17, 2021Date of Patent: May 3, 2022Assignee: Micron Technology, Inc.Inventors: Michele Piccardi, Kalyan C. Kavalipurapu, Xiaojiang Guo
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Patent number: 11205492Abstract: Memories including an array of memory cells, a local access line connected to a plurality of memory cells of the array of memory cells, a global access line, a transistor connected between the global access line and the local access line, and an energy store either selectively connected to a control gate of the transistor, or selectively connected to a control gate of a different transistor connected between the control gate of the transistor and a voltage node configured to receive a reference potential.Type: GrantFiled: December 16, 2020Date of Patent: December 21, 2021Assignee: Micron Technology, Inc.Inventors: Kalyan C. Kavalipurapu, Xiaojiang Guo
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Patent number: 11183247Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.Type: GrantFiled: August 21, 2019Date of Patent: November 23, 2021Assignee: Micron Technology, Inc.Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
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Publication number: 20210272635Abstract: A memory device includes a memory array comprising a plurality of planes, a plurality of voltage generation systems, and a controller. Each voltage generation system is electrically coupled to a corresponding plane. The controller is configured to turn on and warm up each voltage generation system of the plurality of voltage generation systems in response to a first command to access any plane of the plurality of planes and turn off and slowly discharge each voltage generation system of the plurality of voltage generation systems into an idle state in response to no commands being processed. In response to receiving a subsequent command to access any plane of the plurality of planes prior to the voltage generation systems reaching the idle state, a warm up period of the plurality of voltage generation systems is reduced.Type: ApplicationFiled: May 17, 2021Publication date: September 2, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Michele Piccardi, Kalyan C. Kavalipurapu, Xiaojiang Guo
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Publication number: 20210241832Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) upon the selected wordline reaching the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.Type: ApplicationFiled: April 23, 2021Publication date: August 5, 2021Inventors: Allahyar Vahidimowlavi, Kalyan C. Kavalipurapu
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Patent number: 11037636Abstract: A memory device includes a memory array comprising a plurality of planes, a plurality of voltage generation systems, and a controller. Each voltage generation system of the plurality of voltage generation systems is electrically coupled to a corresponding plane of the plurality of planes. The controller is configured to turn on each voltage generation system of the plurality of voltage generation systems in response to a first command to access a first plane of the plurality of planes. The controller is configured to operate the voltage generation system of the plurality of voltage generation systems corresponding to the first plane of the plurality of planes at a first clock frequency, and operate the remaining voltage generation systems of the plurality of voltage generation systems corresponding to the other planes of the plurality of planes at a second clock frequency less than the first clock frequency.Type: GrantFiled: September 10, 2020Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Michele Piccardi, Kalyan C. Kavalipurapu, Xiaojiang Guo
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Patent number: 11004513Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.Type: GrantFiled: January 27, 2020Date of Patent: May 11, 2021Assignee: Micron Technology, Inc.Inventors: Allahyar Vahidimowlavi, Kalyan C. Kavalipurapu
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Publication number: 20210104284Abstract: Memories including an array of memory cells, a local access line connected to a plurality of memory cells of the array of memory cells, a global access line, a transistor connected between the global access line and the local access line, and an energy store either selectively connected to a control gate of the transistor, or selectively connected to a control gate of a different transistor connected between the control gate of the transistor and a voltage node configured to receive a reference potential.Type: ApplicationFiled: December 16, 2020Publication date: April 8, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Kalyan C. Kavalipurapu, Xiaojiang Guo
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Patent number: 10892022Abstract: Methods of operating a memory, and memories configured to perform similar methods, might include initiating discharge of a global access line that is connected to a local access line through a transistor, and electrically floating a control gate of the transistor, in response to a supply voltage decreasing to a first threshold, and initiating discharge of the control gate of the transistor in response to the supply voltage decreasing to a second threshold lower than the first threshold.Type: GrantFiled: August 28, 2019Date of Patent: January 12, 2021Assignee: Micron Technology, Inc.Inventors: Kalyan C. Kavalipurapu, Xiaojiang Guo
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Publication number: 20200411119Abstract: A memory device includes a memory array comprising a plurality of planes, a plurality of voltage generation systems, and a controller. Each voltage generation system of the plurality of voltage generation systems is electrically coupled to a corresponding plane of the plurality of planes. The controller is configured to turn on each voltage generation system of the plurality of voltage generation systems in response to a first command to access a first plane of the plurality of planes. The controller is configured to operate the voltage generation system of the plurality of voltage generation systems corresponding to the first plane of the plurality of planes at a first clock frequency, and operate the remaining voltage generation systems of the plurality of voltage generation systems corresponding to the other planes of the plurality of planes at a second clock frequency less than the first clock frequency.Type: ApplicationFiled: September 10, 2020Publication date: December 31, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Michele Piccardi, Kalyan C. Kavalipurapu, Xiaojiang Guo
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Patent number: 10796773Abstract: A memory device includes a memory array, a plurality of voltage generation systems, and a controller. The memory array includes a plurality of planes. Each voltage generation system of the plurality of voltage generation systems is electrically coupled to a corresponding plane of the plurality of planes. The controller is configured to turn on each voltage generation system of the plurality of voltage generation systems in response to a first command to access a first plane of the plurality of planes.Type: GrantFiled: May 14, 2019Date of Patent: October 6, 2020Assignee: Micron Technolgy, Inc.Inventors: Michele Piccardi, Kalyan C. Kavalipurapu, Xiaojiang Guo
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Publication number: 20200185033Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.Type: ApplicationFiled: January 27, 2020Publication date: June 11, 2020Inventors: Allahyar Vahidimowlavi, Kalyan C. Kavalipurapu
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Patent number: 10546641Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.Type: GrantFiled: December 7, 2018Date of Patent: January 28, 2020Assignee: Micron Technology, Inc.Inventors: Allahyar Vahidimowlavi, Kalyan C. Kavalipurapu
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Publication number: 20190378573Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.Type: ApplicationFiled: August 21, 2019Publication date: December 12, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
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Patent number: 10431310Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.Type: GrantFiled: March 22, 2018Date of Patent: October 1, 2019Assignee: Micron Technology, Inc.Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
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Publication number: 20180308551Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.Type: ApplicationFiled: March 22, 2018Publication date: October 25, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
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Publication number: 20180254089Abstract: In one embodiment, an apparatus comprises a memory array; a sense circuit comprising a first transistor and a sense node coupled to the first transistor and selectively coupled to a memory cell of the memory array via a data line; and a tracking circuit comprising a second transistor having a threshold voltage that is to track a threshold voltage of the first transistor, the tracking circuit to generate at least one sensing parameter of the sense circuit based on the threshold voltage of the second transistor.Type: ApplicationFiled: March 6, 2017Publication date: September 6, 2018Applicant: Intel CorporationInventors: Qiang Tang, Kalyan C. Kavalipurapu
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Patent number: 10049752Abstract: In one embodiment, an apparatus comprises a memory array; a sense circuit comprising a first transistor and a sense node coupled to the first transistor and selectively coupled to a memory cell of the memory array via a data line; and a tracking circuit comprising a second transistor having a threshold voltage that is to track a threshold voltage of the first transistor, the tracking circuit to generate at least one sensing parameter of the sense circuit based on the threshold voltage of the second transistor.Type: GrantFiled: March 6, 2017Date of Patent: August 14, 2018Assignee: Intel CorporationInventors: Qiang Tang, Kalyan C. Kavalipurapu
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Patent number: 9947418Abstract: Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.Type: GrantFiled: April 12, 2016Date of Patent: April 17, 2018Assignee: Micron Technology, Inc.Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
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Publication number: 20170294233Abstract: Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.Type: ApplicationFiled: April 12, 2016Publication date: October 12, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Mark A. Helm, Kalyan C. Kavalipurapu