Patents by Inventor Kalyan Chakravarthy
Kalyan Chakravarthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240176826Abstract: User interface responsiveness is improved using batch interface calls and response processing. To do this, a selection, via a user interface, is obtained of nodes of a hierarchy corresponding to a hierarchical data structure containing information to be presented in the user interface based on the selection. A separate request is sent to a database to obtain information corresponding to each of the nodes. Responses corresponding to a particular request are received from the database. Each response is processed to obtain parsed data in separate threads such that the responses are executable in parallel. The processing of the responses outputs parsed data for the corresponding response. The parsed data is obtained and the parsed data for a particular response is incrementally presented in the user interface as it is obtained.Type: ApplicationFiled: November 29, 2022Publication date: May 30, 2024Inventors: Kalyan Chakravarthy Nannapaneni, Ajay Krishna Uniyal, Srinivas S
-
Publication number: 20240089339Abstract: Techniques and systems are provided for more efficient and reliable caching of responses that are based on API calls to a backend system. The disclosed embodiments use a containerized pipeline that can be linked to each application instance regardless of the specific cloud environment(s) on which the instance is hosted and executed. Instances of the application operating on different cloud environments can access the cached responses from the other environments, thereby reducing or eliminating latency that typically results from the deployment of caching and database solutions across different availability zones in one or more cloud environments.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Inventor: Kalyan Chakravarthy Thatikonda
-
Publication number: 20240070059Abstract: A memory device includes a first array of Non-Volatile Memory (NVM) cells, a second array of logic NVM cells, and a controller. The second array of logic NVM cells stores instructions for accessing the first array of NVM cells. The controller is configured to execute the instructions stored in the second array of logic NVM cells to perform access operations in the first array of NVM cells.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: Vikas Rana, Kalyan Chakravarthy Kavalipurapu
-
Publication number: 20240002534Abstract: Arginase 1 binders that inhibit the activity of human Arginase 1 (hArg1) and comprise human antibodies and antigen-binding fragments thereof comprising human VH and VL are described. These Arginase 1 binders present an alternative mechanism for inhibiting hArg1 activity and highlight the ability to utilize binders as probes in the discovery and development of peptide and small molecule inhibitors for enzymes in general.Type: ApplicationFiled: November 22, 2021Publication date: January 4, 2024Applicant: MERCK SHARP & DOHME LLCInventors: Marc Andre Bailly, Kalyan Chakravarthy, Ghassan Najib Fayad, Laurence Fayadat-Dilman, Esther Kofman, Masahisa Handa, Jennifer E. O'Neil, Rachel Lynn Palte, Giovanna Scapin, Shahriar Shane Taremi
-
Publication number: 20240002535Abstract: Arginase 1 binders that inhibit activity of hArg1, which comprise humanized anti-human Arginase 1 (hArg1) antibodies and antigen-binding fragments thereof obtained from mouse monoclonal antibodies comprising mouse VH and VL, are described. These Arginase 1 binders present an alternative mechanism for inhibiting hArg1 activity and highlight the ability to utilize binders as probes in the discovery and development of peptide and small molecule inhibitors for enzymes in general.Type: ApplicationFiled: November 22, 2021Publication date: January 4, 2024Applicant: MERCK SHARP & DOHME LLCInventors: Marc Andre Bailly, Kalyan Chakravarthy, Ghassan Najib Fayad, Laurence Fayadat-Dilman, Veronica Juan, Esther Kofman, Masahisa Handa, Jennifer E. O'Neil, Rachel Lynn Palte, Giovanna Scapin, Shahriar Shane Taremi
-
Publication number: 20240002533Abstract: Arginase 1 binders comprising human antibodies and antigen-binding fragments thereof that inhibit the activity of human Arginase 1 (hArg1) are described. These Arginase 1 binders present an alternative mechanism for inhibiting hArg1 activity and highlight the ability to utilize binders as probes in the discovery and development of peptide and small molecule inhibitors for enzymes in general.Type: ApplicationFiled: November 22, 2021Publication date: January 4, 2024Applicant: MERCK SHARP & DOHME LLCInventors: Marc Andre Bailly, Kalyan Chakravarthy, Ghassan Najib Fayad, Laurence Fayadat-Dilman, Veronica Juan, Esther Kofman, Heping Lin, Jennifer E. O'Neil, Rachel Lynn Palte, Giovanna Scapin, Hussam Hisham Shaheen, Tao Wang
-
Patent number: 11861236Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.Type: GrantFiled: May 11, 2022Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy C. Kavalipurapu, Chang H. Siau, Shigekazu Yamada
-
Publication number: 20230360709Abstract: A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Inventors: Kalyan Chakravarthy Kavalipurapu, Tomoko Ogura Iwasaki, Erwin E. Yu, Hong-Yan Chen, Yunfei Xu
-
Patent number: 11791003Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.Type: GrantFiled: October 5, 2022Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
-
Publication number: 20230325085Abstract: Memory might include an array of memory cells and a data line selectively connected to a plurality of memory cells of the array of memory cells. The data line might include a first data line segment corresponding to a first subset of memory cells of the plurality of memory cells and a second data line segment corresponding to a second subset of memory cells of the plurality of memory cells. The second data line segment is selectively connected to the first data line segment. A first page buffer might be selectively connected to the first data line segment, and a second page buffer might be selectively connected to the second data line segment.Type: ApplicationFiled: March 6, 2023Publication date: October 12, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Vikas Rana, Kalyan Chakravarthy Kavalipurapu
-
Publication number: 20230306014Abstract: Techniques for data management are described. A file may be saved that includes a representation of an exported database, where the representation may be based on a live database being exported from a computing system via an export operation that spans a time period. A determination that one or more transactions were committed to the live database during the time period may be made. Based on the determination, a log indicating the one or more transactions may be obtained from the computing system. Based on the log, a determination of whether the exported database captured the one or more transactions may be made. Based on the determination, the file may be updated to represent an updated database that reflects an updated version of the live database, the updated version of the live database reflection application of the one or more transactions to the exported database.Type: ApplicationFiled: March 28, 2022Publication date: September 28, 2023Inventor: Kalyan Chakravarthy Akella
-
Patent number: 11749353Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.Type: GrantFiled: May 16, 2022Date of Patent: September 5, 2023Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy Kavalipurapu, Tomoko Ogura Iwasaki, Erwin E. Yu, Hong-Yan Chen, Yunfei Xu
-
Publication number: 20230248871Abstract: The present invention relates to a system (100) for IOT based vertical autoclave machine. The system (100) comprises a plurality of sensors, a control unit, a memory, a digital temperature indicator, a water level indicator, a pressure indicator a digital timer, a cloud and a user interface. The plurality of sensors used to measure the sterilization parameters of autoclave machine. The control unit allows to set the sterilization temperature, pressure and water level of autoclave machine. The digital temperature indicator used to display the temperature of machine accurately. The water level indicator displays the volume of water inside the chamber of machine. The pressure indicator shows the pressure inside the machine for sterilization. The power supply used to provide supply to the system. The cloud enables storing data and files on the internet of autoclave machine. The user interface allows interaction of user with application or with website.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: Surya Kalyan Chakravarthy Nidamanuri, Jafar Ali Ibrahim Syed Masood, Sasmita Samanta
-
Publication number: 20230208715Abstract: Configuration management e.g., configuration validation and remediation (when necessary) of entities in a collective of databases and/or other machines or devices can be burdensome when vendor/cloud provider tools are used to manage the entities due to lack of control over the management. Rather than rely on vendor/cloud provider tools, instead configuration management is offloaded to, e.g., a local API and/or local machine, where configuration deviation detection from an expected configuration is locally determined and remediation needs may be prioritized so higher-priority collective entities are remediated first and other entities deferred. Local processing reduces burdens associated with entity remediation, such as in a cloud-hosted environment having many burdens associated with accessing cloud data and/or databases.Type: ApplicationFiled: December 29, 2021Publication date: June 29, 2023Applicant: salesforce.com, inc.Inventors: Kalyan Chakravarthy THATIKONDA, Ben SIGGERS, Nikita RAJPUT
-
Patent number: 11682462Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums for compensating for charge loss effects. In some examples, a charge loss may be estimated by a charge loss monitor for a particular unit of a NAND device and may be utilized to select a charge loss compensation scheme. The charge loss may be estimated by the charge loss estimation process by determining a reference read voltage and calculating a bit count resulting from a read at that reference read voltage. The number of bits returned may be used to select the particular charge loss compensation scheme.Type: GrantFiled: July 30, 2021Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy C. Kavalipurapu, Jung Sheng Hoei
-
Patent number: 11681522Abstract: A self-healing build pipeline architecture for a software application build job across a distributed computer platform comprises a public API that receives configuration data describing the build job, stores the configuration data in a decentralized database, serves requests to/from a pipeline tracker API, and stores states of build pipelines during the build job. The decentralized database stores the configuration data and a project identifier for the build, and metadata regarding states of the build pipelines collected across the distributed computer platform. The pipeline tracker API runs local to the build environment in the distributed computer platform and sends a build status to public API for updating the decentralized database. For any failures in any of the build pipelines, the state is retrieved from the decentralize database and a new build pipeline is triggered locally that resumes from the failed state to provide a self-healing build pipeline architecture.Type: GrantFiled: October 21, 2021Date of Patent: June 20, 2023Assignee: SALESFORCE, INC.Inventors: Kalyan Chakravarthy Thatikonda, Prabhjot Singh
-
Publication number: 20230129453Abstract: A self-healing build pipeline architecture for a software application build job across a distributed computer platform comprises a public API that receives configuration data describing the build job, stores the configuration data in a decentralized database, serves requests to/from a pipeline tracker API, and stores states of build pipelines during the build job. The decentralized database stores the configuration data and a project identifier for the build, and metadata regarding states of the build pipelines collected across the distributed computer platform. The pipeline tracker API runs local to the build environment in the distributed computer platform and sends a build status to public API for updating the decentralized database. For any failures in any of the build pipelines, the state is retrieved from the decentralize database and a new build pipeline is triggered locally that resumes from the failed state to provide a self-healing build pipeline architecture.Type: ApplicationFiled: October 21, 2021Publication date: April 27, 2023Applicant: salesforce.com, Inc.Inventors: Kalyan Chakravarthy Thatikonda, Prabhjot Singh
-
Patent number: 11637994Abstract: A system comprising a coordinate tracking engine and a video classification engine communicably coupled to a notification engine. The coordinate tracking engine detects that geographical coordinates of a mobile device indicate that an account holder is within a threshold distance of a physical branch of an institution. The notification engine retrieves account information for the account holder. The coordinate tracking engine further detects that the account holder has arrived at the physical branch. The video classification engine captures video frames of an entrance to the physical branch and identifies the account holder. The notification engine further presents account information for the account holder on a display.Type: GrantFiled: July 21, 2021Date of Patent: April 25, 2023Assignee: Bank of America CorporationInventors: Kalyan Chakravarthy Pallapolu, Bharathi Tadepalli
-
Publication number: 20230111193Abstract: Systems, methods, and computer-readable media are disclosed for generating uniform hierarchical views of technical documents irrespective of a file format for the technical document. Metadata definitions may be received that define a technical document hierarchy for the technical document. Based on the metadata definitions, technical data element may be mapped to the technical document hierarchy. The technical document may be generated, the technical document comprising the technical data elements. Based in part on the technical document and the metadata definitions, the uniform hierarchical view may be generated. The uniform hierarchical view may be populated with at least a subset of the technical data elements from the technical document. Once generated, the uniform hierarchical view may be displayed.Type: ApplicationFiled: October 11, 2021Publication date: April 13, 2023Inventors: Ajay Krishna Uniyal, Leena Khatri, Shivendra Kumar Mathur, Aditya Karanth, Kalyan Chakravarthy Nannapaneni, Sampathkumar S, Trimurthulu Kondepudi
-
Patent number: 11567856Abstract: An intelligent determination of code change review assignments and subsequent secured access to the determined assignments. Code changes undergo code change complexity determination which is based on (i) a level of importance of the module(s) in which the changes occur, (ii) the volume of metadata files impacted by the code changes, and (iii) the dependency of the code changes on external modules. A distributed trust computing network is implemented and a code change smart contract which relies on smart contract rules is used to determine and allocate code change review assignments. In this regard, data blocks within a distributed ledger define individual segments/portions of the code change file with each data block identifying a code change review assignment.Type: GrantFiled: June 21, 2021Date of Patent: January 31, 2023Assignee: BANK OF AMERICA CORPORATIONInventors: Kalyan Chakravarthy Pallapolu, Srinath Nelakuditi, Satti Rajeswara Seshareddy