Patents by Inventor Kalyan Chakravarthy Kavalipurapu
Kalyan Chakravarthy Kavalipurapu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240070059Abstract: A memory device includes a first array of Non-Volatile Memory (NVM) cells, a second array of logic NVM cells, and a controller. The second array of logic NVM cells stores instructions for accessing the first array of NVM cells. The controller is configured to execute the instructions stored in the second array of logic NVM cells to perform access operations in the first array of NVM cells.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: Vikas Rana, Kalyan Chakravarthy Kavalipurapu
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Publication number: 20230360709Abstract: A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Inventors: Kalyan Chakravarthy Kavalipurapu, Tomoko Ogura Iwasaki, Erwin E. Yu, Hong-Yan Chen, Yunfei Xu
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Patent number: 11791003Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.Type: GrantFiled: October 5, 2022Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
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Publication number: 20230325085Abstract: Memory might include an array of memory cells and a data line selectively connected to a plurality of memory cells of the array of memory cells. The data line might include a first data line segment corresponding to a first subset of memory cells of the plurality of memory cells and a second data line segment corresponding to a second subset of memory cells of the plurality of memory cells. The second data line segment is selectively connected to the first data line segment. A first page buffer might be selectively connected to the first data line segment, and a second page buffer might be selectively connected to the second data line segment.Type: ApplicationFiled: March 6, 2023Publication date: October 12, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Vikas Rana, Kalyan Chakravarthy Kavalipurapu
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Patent number: 11749353Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.Type: GrantFiled: May 16, 2022Date of Patent: September 5, 2023Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy Kavalipurapu, Tomoko Ogura Iwasaki, Erwin E. Yu, Hong-Yan Chen, Yunfei Xu
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Publication number: 20230022858Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.Type: ApplicationFiled: October 5, 2022Publication date: January 26, 2023Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
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Patent number: 11488677Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.Type: GrantFiled: December 10, 2020Date of Patent: November 1, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
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Publication number: 20220277795Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.Type: ApplicationFiled: May 16, 2022Publication date: September 1, 2022Inventors: Kalyan Chakravarthy Kavalipurapu, Tomoko Ogura Iwasaki, Erwin E. Yu, Hong-Yan Chen, Yunfei Xu
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Publication number: 20220189570Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.Type: ApplicationFiled: December 10, 2020Publication date: June 16, 2022Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
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Patent number: 11335412Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.Type: GrantFiled: August 12, 2020Date of Patent: May 17, 2022Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy Kavalipurapu, Tomoko Ogura Iwasaki, Erwin E. Yu, Hong-Yan Chen, Yunfei Xu
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Publication number: 20210202009Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.Type: ApplicationFiled: August 12, 2020Publication date: July 1, 2021Inventors: Kalyan Chakravarthy Kavalipurapu, Tomoko Ogura Iwasaki, Erwin E. Yu, Hong-Yan Chen, Yunfei Xu