Abstract: A terminal receives one or more input frames comprising one or more logical channels and may generate one or more output frames including the data received in the logical channels. Each logical channel is dispersed throughout the input frame in one or more timeslots, and each logical channel has an associated buffer. The data of each logical channel received from the timeslot(s) of the input frame(s) is stored in the corresponding buffer. The terminal uses channel sequencing for round-robin scheduling to transfer the data of the received logical channels, if present, in each buffer to one or more output frames. Channel sequencing may apply round-robin scheduling of service of buffers in ascending or descending order of non-empty buffers, accounting for newly filled buffers. Channel sequencing generates a binary word, termed a channels service request (CSR) word, with each bit of the CSR word corresponding to a buffer and indicating whether the buffer requests service.

Abstract: In accordance with one embodiment of the invention, a method for compensating frequency offset errors in a communication system comprising the steps of receiving a plurality of signal bursts that correspond to a plurality of transmitted signal bursts. A channel estimation is performed based on at least the predetermined information contained in the transmitted signal bursts. For each received signal sample, a Viterbi decoding is performed using the channel estimations. A final updated Viterbi state cost is calculated for each received signal. A good equalizer quality signal is provided when the final updated Viterbi state cost is below a given threshold. The transmitted signal bursts are then reconstructed from the receive signal bursts, by applying the channel estimation to reencode the decoded signal bursts retrieved from the Viterbi decoder. The quality of the channel estimation is determined based on a given threshold of bit error rate in a plurality of received signal bursts.

Abstract: A Trellis decoder allows for real time decoding of high rate input data more than 10 MHz, with a compact layout and without the need to generate very high speed clocks, by use of a branch metric generator feeding multiple parallel Add/Compare/Select modules, which in turn feed a traceback processor using pre-traceback shift registers and traceback memory. The decoder performs n-state Trellis decoding in real time while simultaneously de-interleaving a multiplexed data stream. The architecture can be expanded to provide programmable length traceback in a fixed number of clock cycles. The invention performs de-interleaving in parallel with the Trellis decoding, and symbols coming out of the decoder need no further processing for de-interleaving. Moreover, the invention allows complete traceback in one symbol period at video rates without the need for very high speed clocks or multi-read port memories. Programmability allows for flexible tradeoff of output error rate and traceback memory space.

Abstract: A digital automatic gain control circuit for a receiver includes an averaging block and an adjustment block. The averaging block receives a length of a digital sample stream that represents an incoming analog signal and produces an absolute average signal. The adjustment block receives the absolute average signal and a reference signal and outputs an adjustment signal for controlling gain. The adjustment signal is based on a difference between the absolute average signal and the reference signal. In an alternative embodiment, a method of controlling gain according to the invention includes the steps of calculating an absolute average of an incoming signal, and comparing the absolute average to a reference to produce an adjustment signal based on a difference between the absolute average and the reference.

Abstract: The invention presents a method of frame synchronization of Digital Video Broadcasting (DVB) data using a temporary storage area (regfile) of substantially smaller dimension than the repetition rate of the sync pattern. Synchronization is achieved by detecting the sync pattern by correlation and determining if the pattern has a fixed repetitive separation. The synchronization scheme of the invention is simple and easily implementable as an integrated circuit, using software and a microprocessor, or as discrete circuitry.

Abstract: An apparatus and method of implementing an equalizer filter configuration including a plurality of memory blocks and a plurality of filter blocks. The respective pluralities of memory blocks and filter blocks are coupled so that the equalizer filter configuration has the capability to process input signal samples. The input signal samples include signal samples selected from the group consisting essentially of complex-valued signal samples and real-valued signal samples.

Abstract: A control method and system for minimizing the on-peak power demand of a residential electric utility user having a plurality of loads is implemented by determining the average energy demand over predetermined sliding time windows and comparing them with a control point. Non-priority loads are shed in an attempt to decrease the demand below the control point. If the energy demand is still above the control point after all non-priority loads are shed, the control point is dynamically adjusted upward and no priority loads are shed. Loads are shed by transmitting bits of information to the loads when the average energy demand over the predetermined time windows increases beyond the control point. Upon receiving bits of information indicating a load should be shed, the receiver deenergizes its load. The bits of information are synchronized to the zero crossing of the AC line. The bits are transmitted simultaneously and periodically.