Abstract: Techniques are provided for mobile platform based detection and prevention (or mitigation) of hearing loss. An example system may include a hearing loss indicator data generation circuit configured to measure hearing loss indicator data associated with use of the device by a user. The hearing loss indicator data may include ambient sound characteristics, user speech volume level and user volume setting of the device. The system may also include an audio context generation circuit configured to estimate context data associated with use of the device. The context data may be based on classification of audio input to the device and on the location of the device. The system may further include an interface circuit configured to collect the hearing loss indicator data and the context data over a selected time period and provide the collected data to a hearing loss analysis system at periodic intervals.

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Abstract: Techniques are provided for mobile platform based detection and prevention (or mitigation) of hearing loss. An example system may include a hearing loss indicator data generation circuit configured to measure hearing loss indicator data associated with use of the device by a user. The hearing loss indicator data may include ambient sound characteristics, user speech volume level and user volume setting of the device. The system may also include an audio context generation circuit configured to estimate context data associated with use of the device. The context data may be based on classification of audio input to the device and on the location of the device. The system may further include an interface circuit configured to collect the hearing loss indicator data and the context data over a selected time period and provide the collected data to a hearing loss analysis system at periodic intervals.

Abstract: Techniques are provided for mobile platform based detection and prevention (or mitigation) of hearing loss. An example system may include a hearing loss indicator data generation circuit configured to measure hearing loss indicator data associated with use of the device by a user. The hearing loss indicator data may include ambient sound characteristics, user speech volume level and user volume setting of the device. The system may also include an audio context generation circuit configured to estimate context data associated with use of the device. The context data may be based on classification of audio input to the device and on the location of the device. The system may further include an interface circuit configured to collect the hearing loss indicator data and the context data over a selected time period and provide the collected data to a hearing loss analysis system at periodic intervals.

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Abstract: Techniques are provided for mobile platform based detection and prevention (or mitigation) of hearing loss. An example system may include a hearing loss indicator data generation circuit configured to measure hearing loss indicator data associated with use of the device by a user. The hearing loss indicator data may include ambient sound characteristics, user speech volume level and user volume setting of the device. The system may also include an audio context generation circuit configured to estimate context data associated with use of the device. The context data may be based on classification of audio input to the device and on the location of the device. The system may further include an interface circuit configured to collect the hearing loss indicator data and the context data over a selected time period and provide the collected data to a hearing loss analysis system at periodic intervals.

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Abstract: A computing platform may include components to determine performance loss values and energy savings values for each of the plurality of regions and/or the memory boundedness value of each of a plurality of regions within an application. The computing platform may provide a user interface for a user to provide a user input, which provides an indication of an acceptable performance loss. For the provided performance loss value, the frequency values may be determined and the processing element may be operated at the frequency values while processing each of the plurality of regions.

Abstract: A computing platform may include components to determine performance loss values and energy savings values for each of the plurality of regions and/or the memory boundedness value of each of a plurality of regions within an application. The computing platform may provide a user interface for a user to provide a user input, which provides an indication of an acceptable performance loss. For the provided performance loss value, the frequency values may be determined and the processing element may be operated at the frequency values while processing each of the plurality of regions.

Abstract: Various embodiments of the present invention relate to methods and systems for optimizing an intermediate code in a compilation logic. The intermediate code is optimized by performing reassociation in software loops. The intermediate code includes at least one critical recurrence cycle. The performance of reassociation in software loops can reduce a critical recurrence cycle in them, which can speed up their execution. The subject method can include the determination of one or more critical recurrence cycles in a software loop. The method can also include the determination of at least one edge in a critical recurrence cycle, with respect to which reassociation can be performed, if one or more pre-determined criteria are met. The method can further include performing reassociation of a dependee and a dependent of an edge. In an embodiment, when one or more pre-determined criteria are met, the logic of the software loop is maintained after performing reassociation of the dependee and the dependent of the edge.

Abstract: A method and system for optimizing the execution of a software loop is provided. The method involves the determination of an edge in a critical recurrence cycle in the software loop. The edge is a dependency link between two instructions and contains a dependee and a dependent. The dependee is an instruction that produces a result, and the dependent is an instruction that uses the result. The method further involves performing predicate promotion of at least one of the dependee and the dependent if one or more pre-determined conditions are met.

Abstract: A method of parallel execution of a first and a second instruction in an in-order processor. Embodiments of the invention enable parallel execution of memory instructions that are stalled by cache memory misses. The in-order processor processes cache memory misses of instructions in parallel by overlapping the first cache memory miss with cache memory misses that occur after the first cache memory miss. Memory-level parallelism in the in-order processor can be increased when more parallel and outstanding cache memory misses are generated.

Abstract: Disclosed are embodiments of a compiler, methods, and system for resource-aware scheduling of instructions. A list scheduling approach is augmented to take into account resource constraints when determining priority for scheduling of instructions. Other embodiments are also described and claimed.

Abstract: An efficient method for software-pipelining (SWP) of loops to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer. In one example embodiment, this is accomplished by spilling and filling multiple computed values, in a register, that are live across multiple stages in a software-pipelined loop, using multiple rotating stack memory locations to reduce compiler-time of SWP, and complexity of the implemented SWP.

Abstract: A method and apparatus are provided for repacking of memory data. For at least one embodiment, data for a plurality of store instructions in a source code program is loaded from memory into the appropriate sub-location of a proxy storage location. The packed data is then written with a single instruction from the proxy storage location into contiguous memory locations.

Abstract: A method that uses software-pipelining to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer, including sparse arrays/matrices. In one example embodiment, this is accomplished by transforming sparse array matrix source code and software-pipelining the transformed source code to reduce recurrence initiation interval, decrease run time, and enhance performance.

Abstract: While translating a program for execution by a first electronic device, instructions are generated based on the program, and a portion of the instructions are analyzed to determine whether a functional unit of the first device will be used by the portion. A special instruction is added to these instructions, that indicates a power down operation to reduce power consumption by the functional unit. The special instruction is compatible with a second electronic device that is not capable of the power down operation. Other embodiments are also described and claimed.