Abstract: A system is provided that orchestrates tasks for a supply chain financial orchestration flow. The system selects tasks to be executed for an event. The system further creates a task group that includes the tasks. The system further assigns a task sequence identifier for each task, where there is a gap between two task sequence identifiers. The system further initiates an execution of a task of the plurality of tasks where the task is eligible for execution. The system further submits a task completion acknowledgement when the execution of the task is complete, where the task completion acknowledgement makes a subsequent task eligible for execution.

Abstract: A system is provided that implements a qualifier. The system selects a qualifier definition that defines the qualifier; where the qualifier definition includes a computer program code definition including one or more conditions. The system further selects a condition from the one or more conditions, where the condition includes a parameter. The system further determines that the parameter is a custom parameter, where a custom parameter indicates that an external computer program is used to generate a value for the custom parameter. The system further invokes the external computer program to generate a value for the custom parameter. The system further evaluates the condition using the generated value. The system further evaluates the qualifier definition using the evaluated condition.

Abstract: A system is provided that communicates tasks. The system generates a task including task payload data, where the task payload data is in a task payload format. The system further transforms the task payload data from the task payload format to a universal format. The system further sends the task payload data and a system parameter to an external interface layer, where the task payload data is sent in the universal format, and where the system parameter identifies an external target system. The system further identifies an external target system and connector service based on the system parameter. The system further sends the task payload data to the connector service, where the task payload data is sent in the universal format.

Abstract: A system is provided that processes supply chain events. The system defines a supply chain event type. The system further configures a supply chain event of the supply chain event type as a task generating event, where the task generating event indicates that one or more tasks that are defined for a supply chain financial orchestration flow are to be executed, and where the supply chain financial orchestration flow defines a trade relationship between a first entity and a second entity. The system further receives a supply chain event associated with the supply chain financial orchestration flow. The system further determines whether the supply chain event is a task generating event. The system further executes the one or more tasks that are defined for the supply chain financial orchestration flow where the supply chain event is a task generating event.

Abstract: A method and apparatus for storing and classifying packets transmitted over a network to a processor in a low power mode. The processor receives and classifies the packets as interesting or not interesting. Uninteresting packets are discarded while interesting packets are stored in memory. For the first interesting packet received, a receive timer is activated and for every interesting packet received a counter is incremented. A transmit timer is activated when the processor enters the low power mode. When either the receive timer expires, the transmit timer expires or the counter reaches a threshold value then a wake-up interrupt is asserted.

Abstract: A method and apparatus for storing and classifying packets transmitted over a network to a processor in a low power mode. The processor receives and classifies the packets as interesting or not interesting. Uninteresting packets are discarded while interesting packets are stored in memory. For the first interesting packet received, a receive timer is activated and for every interesting packet received a counter is incremented. A transmit timer is activated when the processor enters the low power mode. When either the receive timer expires, the transmit timer expires or the counter reaches a threshold value then a wake-up interrupt is asserted.

Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source means includes of a controllable digital fractional divider means receiving a control value from digital comparator means and a clock input from a digital clock synthesizer means driven by a fixed oscillator means.

Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source includes of a controllable digital fractional divider receiving a control value from digital comparator and a clock input from a digital clock synthesizer driven by a fixed oscillator.

Abstract: An improved fractional divider that comprises an integer value storage means containing the integer part of the division value ‘K’ connected to the input of a programmable counter means that is configured for a count value of ‘K’ or ‘K+1’ depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces the count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value.

Abstract: The invention provides method and apparatus to reduce access time in synchronous FIFOs with zero latency overheads. The FIFO buffer includes a FIFO circuit capable of storing ‘n’ data words, each ‘m’ bits wide, having an ‘m’ bit wide data input terminal. Furthermore, the FIFO buffer includes a read data set selection circuit connected to the data output terminals of the FIFO circuit and having two data output terminals providing simultaneous access to a selected storage location at an odd address and an even address. An odd read pointer generating circuit provides the selection input to the data selection circuit for selecting data at an odd read address of the read data selection circuit, while an even read pointer generating circuit provides the input for selecting data at an even read address. A multiplexer coupled to each of the two data output terminals of the read data set selection circuit selects one of its outputs as the final output of the FIFO.

Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source means includes of a controllable digital fractional divider means receiving a control value from digital comparator means and a clock input from a digital clock synthesizer means driven by a fixed oscillator means.

Abstract: An improved fractional divider that comprises an integer value storage means containing the integer part of the division value ‘K’ connected to the input of a programmable counter means that is configured for a count value of ‘K’ or ‘K+1’ depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces the count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value.

Abstract: A glitch filter includes a storage element for storing a current state, which is the output of the filter. An output of the storage element is-connected to one input of a state comparator. Another input of the state comparator is connected to an input signal. A programmable clock delay is connected between the state comparator and the storage element. The programmable clock delay may provide a programmed duration independent of the technology used for implementation. The glitch filter is arranged such that the input signal is stored as the new current state in the storage element only if the input signal changes and then remains unchanged for the programmed duration.

Abstract: A glitch filter includes a storage element for storing a current state, which is the output of the filter. An output of the storage element is connected to one input of a state comparator. Another input of the state comparator is connected to an input signal. A programmable clock delay is connected between the state comparator and the storage element. The programmable clock delay may provide a programmed duration independent of the technology used for implementation. The glitch filter is arranged such that the input signal is stored as the new current state in the storage element only if the input signal changes and then remains unchanged for the programmed duration.