Abstract: Three-dimensional integrated circuit structures providing thermoelectric cooling and methods for cooling such integrated circuit structures are disclosed. In one exemplary embodiment, a three-dimensional integrated circuit structure includes a plurality of integrated circuit chips stacked one on top of another to form a three-dimensional chip stack, a thermoelectric cooling daisy chain comprising a plurality of vias electrically connected in series with one another formed surrounding the three-dimensional chip stack, a thermoelectric cooling plate electrically connected in series with the thermoelectric cooling daisy chain, and a heat sink physically connected with the thermoelectric cooling plate.

Abstract: Cooling devices for SOI wafers and methods for forming the devices are presented. A substrate having a top surface layer, a support substrate and an insulator layer isolating the top surface layer from the support substrate is provided. At least one device is disposed in the top surface layer of the substrate. The IC includes a cooling device. The cooling device includes a doped layer which is disposed in a top surface of the support substrate, and a RDL layer disposed within the support substrate below the doped layer for providing connections to hotspots in the doped layer to facilitate thermoelectric conduction of heat in the hotspots away from the hotspots.

Abstract: Cooling devices for SOI wafers and methods for forming the devices are presented. A substrate having a top surface layer, a support substrate and an insulator layer isolating the top surface layer from the support substrate is provided. At least one device is disposed in the top surface layer of the substrate. The IC includes a cooling device. The cooling device includes a doped layer which is disposed in a top surface of the support substrate, and a RDL layer disposed within the support substrate below the doped layer for providing connections to hotspots in the doped layer to facilitate thermoelectric conduction of heat in the hotspots away from the hotspots.

Abstract: Integrated circuits with selectively stressed semiconductor-on-insulator (SOI) body contacts and methods for fabricating integrated circuits with selectively stressed SOI body contacts are provided. An exemplary method for fabricating an integrated circuit includes forming a channel region and a body contact overlying and/or in an SOI substrate. Further, the method includes selectively applying a first stress to the source/drain region in a longitudinal direction. Also, the method includes selectively applying a second stress to the body contact in a lateral direction perpendicular to the longitudinal direction.

Abstract: Integrated circuits with selectively stressed semiconductor-on-insulator (SOI) body contacts and methods for fabricating integrated circuits with selectively stressed SOI body contacts are provided. An exemplary method for fabricating an integrated circuit includes forming a channel region and a body contact overlying and/or in an SOI substrate. Further, the method includes selectively applying a first stress to the source/drain region in a longitudinal direction. Also, the method includes selectively applying a second stress to the body contact in a lateral direction perpendicular to the longitudinal direction.

Abstract: A method of forming shallow trench isolations wherein trench oxide grooving due to etch stop layer etching is eliminated by the formation of a liner oxidation overlying a polysilicon layer. A semiconductor substrate is provided. A pad oxide layer is grown. A polysilicon layer is deposited. Optionally, the polysilicon layer may be ion implanted to increase the oxidation rate. A silicon nitride layer is deposited. The silicon nitride layer, the polysilicon layer, the pad oxide layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations. A liner oxidation layer is grown overlying the semiconductor substrate, the pad oxide layer, and the polysilicon layer inside the trenches. A trench oxide layer is deposited overlying said silicon nitride layer and filling said trenches. The trench oxide layer is polished down to the silicon nitride layer. The silicon nitride layer, the polysilicon layer, the pad oxide layer are etched away.