Patents by Inventor Kam Law

Kam Law has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030219662
    Abstract: Charge transport compounds are described that have a multiple number of hydrazone-bridged heterocyclic groups (especially julolidine groups, carbazole groups, triarylamine groups and (N,N-disubstituted)arylamine groups such as dialkarylamine groups (e.g. dimethylphenylamine; methylethylphenylamine, dipropylphenylamine, ethylepropylphenylamine, ethylbutylnaphthylamine, etc.), alkyldiarylamine groups (e.g. methyldiphenylamino, ethyldiphenylamino, etc), and triarylamino groups (e.g., triphenyl amino, trinaphthylamino, etc)) connected by a central bridging group.
    Type: Application
    Filed: May 30, 2003
    Publication date: November 27, 2003
    Applicant: SAMSUNG Electronics Co. Ltd.
    Inventors: Nusrallah Jubran, Zbigniew Tokarski, Kam Law, Vytautas Getautis, Jonas Sidaravicius, Osvaldas Paliulis, Valentas Gaidelis, Vygintas Jankauskas
  • Publication number: 20030194825
    Abstract: A method of gate metal layer deposition using a cyclical deposition process for thin film transistor applications is described. The cyclical deposition process comprises alternately adsorbing a metal-containing precursor and a reducing gas on a substrate. Thin film transistors, such as a bottom-gate transistor or a top-gate transistor, including a gate layer, may be formed using such cyclical deposition techniques.
    Type: Application
    Filed: April 10, 2002
    Publication date: October 16, 2003
    Inventors: Kam Law, Quan Yuan Shang, William Reid Harshbarger, Dan Maydan
  • Publication number: 20030189232
    Abstract: A method of passivation layer deposition using a cyclical deposition process is described. The cyclical deposition process may comprise alternately adsorbing a silicon-containing precursor and a reactant gas on a substrate structure. Thin film transistors, such as a bottom-gate transistor or a top-gate transistor, including a silicon-containing passivation layer, may be formed using such cyclical deposition techniques.
    Type: Application
    Filed: April 9, 2002
    Publication date: October 9, 2003
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Kam Law, Quan Yuan Shang, William Reid Harshbarger, Dan Maydan
  • Publication number: 20030189208
    Abstract: A method of silicon layer deposition using a cyclical deposition process. The cyclical deposition process comprises alternately adsorbing a silicon-containing precursor and a reducing gas on a substrate structure. Thin film transistors, such as for example a bottom-gate transistor or a top-gate transistor, including one or more silicon layers may, be formed using such cyclical deposition techniques.
    Type: Application
    Filed: April 5, 2002
    Publication date: October 9, 2003
    Inventors: Kam Law, Quan-Yang Shang, William Reid Harshbarger, Dan Maydan
  • Publication number: 20020115269
    Abstract: Deposition methods for preparing amorphous silicon based films with controlled resistivity and low stress are described. Such films can be used as the interlayer in FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition methods described in the present invention employ the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used. In one embodiment, an amorphous silicon-based film is formed by introducing into a deposition chamber a silicon-based volatile, a conductivity-increasing volatile including one or more components for increasing the conductivity of the amorphous silicon-based film, and a conductivity-decreasing volatile including one or more components for decreasing the conductivity of the amorphous silicon-based film.
    Type: Application
    Filed: November 2, 2001
    Publication date: August 22, 2002
    Applicant: Applied Materials, Inc.
    Inventors: William R. Harshbarger, Takako Takehara, Jeff C. Olsen, Regina Qiu, Yvonne LeGrice, Guofu J. Feng, Robert M. Robertson, Kam Law
  • Patent number: 6352910
    Abstract: Deposition methods for preparing amorphous silicon based films with controlled resistivity and low stress are described. Such films can be used as the interlayer in FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition methods described in the present invention employ the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used. In one embodiment, an amorphous silicon-based film is formed by introducing into a deposition chamber a silicon-based volatile, a conductivity-increasing volatile including one or more components for increasing the conductivity of the amorphous silicon-based film, and a conductivity-decreasing volatile including one or more components for decreasing the conductivity of the amorphous silicon-based film.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: March 5, 2002
    Assignee: Applied Komatsu Technology, Inc.
    Inventors: William R. Harshbarger, Takako Takehara, Jeff C. Olsen, Regina Qiu, Yvonne LeGrice, Guofu J. Feng, Robert M. Robertson, Kam Law
  • Patent number: 6207304
    Abstract: An improved method of producing silicon oxy-nitride films is provided by utilizing a reactant gas mixture of silane, nitrous oxide and nitrogen at a low deposition temperature of less than 250° C. by flowing the reactant gas mixture through a gas inlet manifold which is also an upper electrode in a plasma-enhanced chemical vapor deposition chamber. The gas inlet manifold is the upper plate of a parallel plate plasma chamber for communicating the reactant gas into the chamber. The plate has a plurality of apertures, each comprising an outlet at a chamber or processing side of the plate and an inlet spaced from the processing side, with the outlet being larger than the inlet for enhancing the dissociation and reactivity of the gas.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: March 27, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Kam Law, Jeff Olsen
  • Patent number: 5928732
    Abstract: A method of producing silicon oxy-nitride films is provided by utilizing a reactant gas mixture of silane, nitrous oxide and nitrogen at a low deposition temperature of less than 250.degree. C. by flowing the reactant gas mixture through a gas inlet manifold which is also an upper electrode in a plasma-enhanced chemical vapor deposition chamber. The gas inlet manifold is the upper plate of a parallel plate plasma chamber for communicating the reactant gas into the chamber. The plate has a plurality of apertures, each comprising an outlet at a chamber or processing side of the plate and an inlet spaced from the processing side, with the outlet being larger than the inlet for enhancing the dissociation and reactivity of the gas.
    Type: Grant
    Filed: April 10, 1995
    Date of Patent: July 27, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Kam Law, Jeff Olsen
  • Patent number: 5902650
    Abstract: A method of depositing an amorphous silicon based film that has controlled resistivity in between that of an intrinsic amorphous silicon and an n.sup.+ doped amorphous silicon on a substrate for an electronic device by a chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process.
    Type: Grant
    Filed: July 11, 1995
    Date of Patent: May 11, 1999
    Assignee: Applied Komatsu Technology, Inc.
    Inventors: Jeff Feng, Robert Robertson, Kam Law
  • Patent number: 5892328
    Abstract: A plasma-based generator for use with a power source including a plasma tube having a hollow tube body in which a plasma is generated by the power source; a first support structure supporting a downstream end of the plasma tube; and a second support structure holding an upstream end of the plasma tube, the second support structure connected to the first support structure, the second support structure including an expansion joint which changes its length to accommodate a lengthening and a shortening of the plasma tube due to its thermal expansion and contraction when plasma processing is performed within the plasma tube.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: April 6, 1999
    Assignee: Applied Komatsu Technology Inc.
    Inventors: Quanyuan Shang, Kam Law, Dan Maydan
  • Patent number: 5861197
    Abstract: A plasma enhanced chemical vapor deposition process for depositing conformal silicon oxide thin films useful to make thin film transistors which have stable electrical properties and low charge centers onto a substrate comprising flowing a precursor gas mixture of silane and nitrous oxide, the latter at a high rate, at a pressure of at least about 0.8 torr and a temperature of from about 250.degree. to 350.degree. C. The effective volume of the reaction region between the gas manifold inlet and the substrate during processing is kept small.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: January 19, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Kam Law, Robert Robertson, Guofu Jeff Feng
  • Patent number: 5851602
    Abstract: A plasma enhanced chemical vapor deposition process for depositing conformal silicon oxide thin films useful to make thin film transistors which have stable electrical properties and low charge centers onto a substrate comprising flowing a precursor gas mixture of silane and nitrous oxide, the latter at a high rate, at a pressure of at least about 0.8 torr and a temperature of from about 250.degree. to 350.degree. C. The effective volume of the reaction region between the gas manifold inlet and the substrate during processing is kept small.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: December 22, 1998
    Assignee: Applied Materials, Inc.
    Inventors: Kam Law, Robert Robertson, Jeffrey Feng
  • Patent number: 5589233
    Abstract: A method of depositing layers of intrinsic amorphous silicon and doped amorphous silicon sequentially on a substrate in the same CVD chamber without incurring a dopant contamination problem. The method can be carried out by first depositing an additional layer of a dielectric insulating material prior to the deposition process of the intrinsic amorphous silicon layer. The additional layer of insulating material deposited on the substrate should have a thickness such that residual insulating material coated on the chamber walls is sufficient to cover the residual dopants on the chamber walls left by the deposition process of the previous substrate. This provides a clean environment for the next deposition process of an intrinsic amorphous silicon layer on a substrate in the same CVD chamber.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 31, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Kam Law, Robert Robertson, Guofu J. Feng
  • Patent number: 5380566
    Abstract: A method of limiting sticking of a body (substrate) to a susceptor after the body has been coated with a layer in a deposition chamber by plasma chemical vapor deposition includes subjecting the coated body to a plasma of an inactive gas, e.g., hydrogen, nitrogen, argon or ammonia, which does not adversely affect the coating and does not add additional layers to the body. After the coated body is subjected to the plasma of the inactive gas, the body is separated from the susceptor.
    Type: Grant
    Filed: June 21, 1993
    Date of Patent: January 10, 1995
    Assignee: Applied Materials, Inc.
    Inventors: Robert Robertson, Marc M. Kollrack, Angela T. Lee, Kam Law, Dan Maydan