Patents by Inventor Kam Wing Li
Kam Wing Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9483416Abstract: A method of processor operation using an integrated circuit (IC) can include loading encrypted program code into the IC through a configuration port of the IC and decrypting the encrypted program code using configuration circuitry of the IC. Decryption of the encrypted program code can result in decrypted program code which can be provided to a target destination.Type: GrantFiled: October 21, 2010Date of Patent: November 1, 2016Assignee: XILINX, INC.Inventors: Ting Lu, Stephen M. Trimberger, Eric E. Edwards, Weiguang Lu, Kam-Wing Li
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Patent number: 8248883Abstract: A system for implementing a non-volatile input/output (I/O) device based memory can include an interface configured to receive a processor request specifying a data unit. The data unit can be specified by a processor address. The system can include an address-data converter coupled to the interface. The address-data converter can be configured to correlate the processor address of the data unit to a data block within the non-volatile I/O device. The system further can include an I/O controller coupled to the address-data converter. The I/O controller can be configured to issue a non-volatile I/O device command specifying the data block to the non-volatile I/O device.Type: GrantFiled: August 31, 2010Date of Patent: August 21, 2012Assignee: Xilinx, Inc.Inventors: Ting Lu, Kam-Wing Li, Anatoly Belkin, Ahmad R. Ansari
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Patent number: 8185720Abstract: A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar interconnect. The crossbar interconnect provides pipelines for coupling the hardwired core to the programmable circuitry. The microprocessor, the crossbar interconnect, and the memory controller interface are all capable of operating at a first frequency of operation, and the memory controller interface is further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation. The crossbar interconnect is configured to direct transactions initiated by the microprocessor to the memory controller interface for accessing one or more memory devices coupled to the memory controller interface via a memory controller.Type: GrantFiled: March 5, 2008Date of Patent: May 22, 2012Assignee: Xilinx, Inc.Inventors: Ahmad R. Ansari, Jeffery H. Appelbaum, Kam-Wing Li, James J. Murray, Kathryn S. Purcell, Alex S. Warshofsky
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Patent number: 8161212Abstract: An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request and a first memory coupled to the interface. The first memory can be configured to store a data unit specified by the source request. The system can include an I/O device controller coupled to the interface. The I/O device controller can be configured to correlate the source request with a plurality of I/O device requests and initiate sending of the plurality of I/O device requests to the plurality of non-volatile I/O devices in parallel. The system also can include a decoder coupled to the first memory and the I/O device controller. The decoder can be configured to receive data from the plurality of non-volatile I/O devices in parallel.Type: GrantFiled: September 22, 2010Date of Patent: April 17, 2012Assignee: Xilinx, Inc.Inventors: Ting Lu, Kam-Wing Li, Bradley L. Taylor
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Patent number: 8006021Abstract: A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.Type: GrantFiled: March 27, 2008Date of Patent: August 23, 2011Assignee: Xilinx, Inc.Inventors: Kam-Wing Li, Jeffery H. Appelbaum, Ahmad R. Ansari
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Patent number: 7970977Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.Type: GrantFiled: January 30, 2009Date of Patent: June 28, 2011Assignee: Xilinx, Inc.Inventors: Kam-Wing Li, Ahmad R. Ansari, Sanford L. Helton, Tomai Knopp, Khang Kim Dao, Jeffrey H. Seltzer
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Patent number: 7737725Abstract: A device control register controller for a processor block Application Specific Integrated Circuit (“ASIC”) core is described. Device control register slave blocks are coupled to the device control register controller and have access to device registers for a plurality of interfaces of the processor block ASIC core. A master device interface is for coupling at least one slave device external to the processor block ASIC core to the device control register controller. A slave device interface is for coupling a master device external to the processor block ASIC core to the device control register controller.Type: GrantFiled: April 4, 2008Date of Patent: June 15, 2010Assignee: Xilinx, Inc.Inventors: Ahmad R. Ansari, Kam-Wing Li
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Patent number: 7730244Abstract: Command translation of burst commands is described. A slave processor local bus (“PLB”) bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB bridge, has any of a plurality of command bus widths. A burst command is issued via a command bus, having a command bus width of the plurality, from the master device for the slave PLB bridge. The burst command is converted to a native bus width of the slave processor logic block if the command bus width is not equal to the native bus width. The burst command is translated if execution of the burst command will exceed the data size threshold and passed without the translating if the execution of the burst command will not exceed the data size threshold.Type: GrantFiled: March 27, 2008Date of Patent: June 1, 2010Assignee: XILINX, Inc.Inventors: Ahmad R. Ansari, Jeffery H. Appelbaum, Kam-Wing Li, James J. Murray
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Patent number: 7715443Abstract: The techniques described herein allow a more efficient transmuxing operation for transferring data from a synchronous domain (e.g., SONET) to a plesiochronous (e.g., PDH) domain as compared to the prior art, in which extraction of data streams, jitter filtering and stuff bit generation are processed separately. The techniques described herein include extraction of data from the plesiochronous data stream without complete extraction of the underlying native data stream. Filtering is performed based on synchronous timing, which results in a simpler filter design.Type: GrantFiled: December 5, 2003Date of Patent: May 11, 2010Assignee: Meriton Networks US Inc.Inventor: Kam-Wing Li
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Patent number: 6578153Abstract: In one aspect, the present invention provides a method of communicating across a serial line 26. In this method, n parallel streams of data 30 are to be received at a destination 20. In a first embodiment, the n parallel streams of data 30 characterized in that one of streams of data includes a unique characteristic that can be used to distinguish that one from each of the other streams of data. In a second embodiment, each of the n streams of data 30 are in a particular pattern that includes a detectable characteristic. At the destination 20, the unique characteristic and/or detectable characteristic can be detected to correct space and/or time errors in the streams of data. For example, the destination 20 might be a receiver that includes a serial-to-parallel converter 28 and calibration circuitry 34.Type: GrantFiled: March 16, 2000Date of Patent: June 10, 2003Assignee: Fujitsu Network Communications, Inc.Inventors: Wayne Robert Sankey, Kyl Scott, Osman Koyuncu, Kam-Wing Li, Ritesh Dhirajlal Sojitra
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Patent number: 4508958Abstract: An improved ceiling fan including a housing to be hung down from a ceiling and a motor having a stationary stator and a rotatable rotor which rotates a number of blades to create a stream of air. One or more electrical heating elements are positioned within the housing and around the outside of the rotor. A radial fan arrangement generates a flow of air through the housing, over the heating elements, and out into the stream of air created by the rotation of the blades.Type: GrantFiled: December 16, 1982Date of Patent: April 2, 1985Assignee: Wing Tat Electric Mfg. Co. Ltd.Inventors: Frederick S. C. Kan, Kam Wing Li, Kong Ping P. Lau