Abstract: Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.

Abstract: Methods, circuits and systems for converting of a non-predicated asynchronous netlist to a predicated asynchronous netlist are described. These may operate to identify one or more portions of an asynchronous netlist corresponding to a partially utilized portion of an asynchronous circuit. The asynchronous netlist may be modified to control the partially utilized portion. Additional methods, circuits, and systems are disclosed.

Abstract: Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.

Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Abstract: Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.

Abstract: Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.

Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Abstract: Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.

Abstract: Methods, circuits and systems for converting of a non-predicated asynchronous netlist to a predicated asynchronous netlist are described. These may operate to identify one or more portions of an asynchronous netlist corresponding to a partially utilized portion of an asynchronous circuit. The asynchronous netlist may be modified to control the partially utilized portion. Additional methods, circuits, and systems are disclosed.

Abstract: A method of implementing a circuit design for a target device can include assigning load pins of a high fanout signal of a placed circuit design into a plurality of windows according to a location of each load pin on the target device. A source of the high fanout signal can be replicated, wherein each window is associated with a source of the high fanout signal. For each source of the high fanout signal, the source can be connected to load pins of the window associated with the source and the source can be placed within the window associated with the source. The placed circuit design can be output.

Abstract: A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding partitions of the circuit design, selecting a circuit element of the circuit design, and selecting a candidate location within a logic boundary on the target PLD. The method also can include validating the candidate location for the selected circuit element, at least in part, according to whether the selected circuit element belongs to a same partition of the circuit design as at least one other circuit element already placed within the logic boundary. The selected circuit element can be selectively placed at the candidate location according to the validation.

Abstract: A method of optimizing a portion of a circuit design for a target device can include identifying a critical region from a plurality of regions after an initial placement of the circuit design. The critical region can be defined, at least in part, by at least one input block and at least one output block. Blocks of the critical region can be relocated to different sites within the critical region. The method further can include evaluating the relocation of blocks of the critical region according to a cost function and continuing to relocate blocks and evaluate the relocation of blocks in the critical region until at least one exit criterion is met.

Abstract: A method of placing a circuit design for a target device can include identifying a critical region having at least one input block and at least one output block and determining a line starting at the input block and extending to the output block. Blocks of the critical region can be assigned to sites located on, or proximate to, the line according to connectivity.

Abstract: A method of estimating congestion for a programmable logic device can include calculating a number of fan-in paths for each resource in the programmable logic device and calculating a number of fan-out paths for each resource in the programmable logic device. For each resource of the programmable logic device, a number of paths having different path characteristics can be determined and a probability can be assigned thereto. One or more measures of congestion can be computed according to the determining step.

Abstract: Circuit implementations and test methods enable the testing of lookup table (LUT) input paths, “stuck at” memory cell values, and carry chains. One method includes storing a first bit pattern in each LUT, configuring the carry chain to perform a wide AND function of the LUT outputs, and cycling the inputs of each LUT while comparing the carry chain output to an expected value and reporting the PLD faulty if a difference is detected. The carry chain is configured to perform a wide OR function, and the cycling step is repeated. The bit pattern within each LUT is changed to the complement of the first bit pattern by providing a series of shift commands or by otherwise storing new values in the LUT, and the configuring and cycling steps are repeated. The invention also provides PLD circuit implementations that can be used to perform the described methods.

Abstract: Circuits that can be optionally programmed to function as lookup tables (LUTs) or wide multiplexers, and integrated circuits including these programmable circuits. A function select multiplexer is included between each memory cell and the corresponding data input terminal of a first multiplexer. Each function select multiplexer has a first data input terminal coupled to the corresponding memory cell, a second data input terminal coupled to an external input terminal, and a select terminal controlled by a value stored in a function select memory cell. When a first value is stored in the function select memory cell, the programmable circuit functions in the same fashion as a known LUT. When a second value is stored in the function select memory cell, the programmable circuit functions as a wide multiplexer, with the data input values being provided by the external input terminals.

Abstract: Method and apparatus for post-placement optimization of resources for connections is described. To optimize resource placement, search windows are generated responsive to driver and load components, as well as to a connection between the driver and load components. Adding in a straight-line path search window may be used as an alternative where a bypassed resource is to be relocated. Using connection-based optimization in combination with driver- and resource-based optimization results in improved optimization with negligible impact on runtime.

Abstract: A method (400) of placing a circuit design can include the steps of identifying topological levels of a circuit design representation (415) and determining an arrival time for each input signal to a look up table within a circuit design representation (420). The propagation delay associated with each pin of the look up table can be identified (420) such that the input signals of the look up table can be ordered according to the arrival times of each input signal and the propagation delay of each pin of the look up table (435). The method can continue processing each look up table of an identified topological level (440) as well as each topological level of the circuit design representation (455).

Abstract: A method and apparatus for automatic, timing-driven implementation of a circuit design. In one embodiment, the different phases of implementing a circuit design are iteratively performed using timing constraints that are automatically and dynamically generated in each iteration. The process aids in identifying and achieving a maximum performance level of the implemented design. In another embodiment, selected numbers of critical connections are used to dynamically vary the timing constraint. In general, a number of connections is automatically selected from the circuit design and used to derive a new timing constraint to be applied in the next iteration. Slack values associated with paths in the design are also used in deriving the new timing constraint.

Abstract: The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.