Abstract: A MOS precision capacitor is formed in an integrated circuit including a p-mos and n-mos transistor without adding to the process steps used in forming the p-mos and n-mos transistor. The MOS precision capacitor includes a n-well formed concurrently with a n-well of the p-mos transistor, a n-type region formed concurrently with a threshold adjust region of the p-mos transistor, an oxide layer formed concurrently with gate oxide layers of the p-mos and n-mos transistors, a first electrode formed over the n-type region, at least one n+ region formed concurrently with source and drain regions of the n-mos transistor by self aligning to the sidewall of the first electrode, and a second electrode connected to the at least one n+ region.

Abstract: A MOS precision capacitor is formed in an integrated circuit including a p-mos and n-mos transistor without adding to the process steps used in forming the p-mos and n-mos transistor. The MOS precision capacitor includes a n-well formed concurrently with a n-well of the p-mos transistor, a n-type region formed concurrently with a threshold adjust region of the p-mos transistor, an oxide layer formed concurrently with gate oxide layers of the p-mos and n-mos transistors, a first electrode formed over the n-type region, at least one n+ region formed concurrently with source and drain regions of the n-mos transistor by self aligning to the sidewall of the first electrode, and a second electrode connected to the at least one n+ region.

Abstract: Electrostatic discharge protection circuitry is used to protect a MOS feedback element placed between pins such as oscillator input and an oscillator output pins. The ESD protection circuitry may include a first metal-oxide-silicon field effect transistor whose source and gate are electrically connected to the oscillator input pin and whose drain is electrically connected to the oscillator output pin and a second metal-oxide-silicon field effect transistor whose source and gate are electrically connected to the oscillator output pin and whose drain is electrically connected to the oscillator input pin.

Abstract: An Electrically Alterable Read Only Memory device including at least one cell in a substrate having source and drain channels with a memory gate region therebetween with the substrate in the memory gate region having therein a first impurity material of a first conductivity type to establish a desired write threshold voltage and a second impurity material of a second conductivity type opposite to said first type to tailor the surface concentration profiles of the impurity material in the memory gate region of the substrate.