Patents by Inventor Kamatchi Subramanian
Kamatchi Subramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8896070Abstract: The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.Type: GrantFiled: April 13, 2012Date of Patent: November 25, 2014Assignee: Seagate Technology LLCInventors: Hyung-Kyu Lee, YoungPil Kim, Peter Nicholas Manos, Maroun Khoury, Dadi Setiadi, Chulmin Jung, Hsing-Kuen Liou, Paramasiyan Kamatchi Subramanian, Yongchul Ahn, Jinyoung Kim, Antoine Khoueir
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Publication number: 20130302948Abstract: A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.Type: ApplicationFiled: July 22, 2013Publication date: November 14, 2013Applicant: SEAGATE TECHNOLOGY LLCInventors: Dadi Setiadi, Peter Nicholas Manos, Hsing-Kuen Liou, Paramasivan Kamatchi Subramanian, Young Pil Kim, Hyung-Kyu Lee, Maroun Georges Khoury, Chulmin Jung
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Publication number: 20120199915Abstract: The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.Type: ApplicationFiled: April 13, 2012Publication date: August 9, 2012Applicant: Seagate Technology LLCInventors: Hyung-Kyu Lee, YoungPil Kim, Peter Nicholas Manos, Maroun Khoury, Dadi Setiadi, Chulmin Jung, Hsing-Kuen Liou, Paramasiyan Kamatchi Subramanian, Yongchul Ahn, Jinyoung Kim, Antoine Khoueir
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Patent number: 8183126Abstract: Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.Type: GrantFiled: July 13, 2009Date of Patent: May 22, 2012Assignee: Seagate Technology LLCInventors: Hyung-Kyu Lee, YoungPil Kim, Peter Nicholas Manos, Maroun Khoury, Dadi Setiadi, Chulmin Jung, Hsing-Kuen Liou, Paramasiyan Kamatchi Subramanian, Yongchul Ahn, Jinyoung Kim, Antoine Khoueir
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Publication number: 20120074466Abstract: A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.Type: ApplicationFiled: September 28, 2010Publication date: March 29, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Dadi Setiadi, Peter Nicholas Manos, Hsing-Kuen Liou, Paramasivan Kamatchi Subramanian, Young Pil Kim, Hyung-Kyu Lee, Maroun Georges Khoury, Chulmin Jung
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Publication number: 20110006377Abstract: Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Hyung-Kyu Lee, YoungPil Kim, Peter Nicholas Manos, Maroun Khoury, Dadi Setiadi, Chulmin Jung, Hsing-Kuen Liou, Paramasiyan Kamatchi Subramanian, Yongchul Ahn, Jinyoung Kim, Antoine Khoueir
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Patent number: 7504287Abstract: A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.Type: GrantFiled: March 22, 2007Date of Patent: March 17, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Sven Beyer, Kamatchi Subramanian
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Publication number: 20080233738Abstract: A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.Type: ApplicationFiled: March 22, 2007Publication date: September 25, 2008Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Sven BEYER, Kamatchi SUBRAMANIAN
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Patent number: 7288482Abstract: Methods of etching silicon nitride material, and more particularly, etching nitride selective to silicon dioxide or silicide, are disclosed. The methods include exposing a substrate having silicon nitride thereon to a plasma including at least one fluorohydrocarbon and a non-carbon containing fluorine source such as sulfur hexafluoride (SF6). The plasma may also include oxygen (O2) and the fluorohydrocarbons may include at least one of: trifluoromethane (CHF3), difluoromethane (CH2F2), and methyl fluoride (CH3F). In an alternative embodiment, the plasma includes one of hydrogen (H2) and nitrogen trifluoride (NF3) and one of tetrafluoromethane (CF4) and octafluorocyclobutane (C4F8). The methods are preferably carried out using a low bias voltage, e.g. <100 V.Type: GrantFiled: May 4, 2005Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Siddhartha Panda, Richard Wise, Srikanteswara Dakshina Murthy, Kamatchi Subramanian
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Publication number: 20060252269Abstract: Methods of etching silicon nitride material, and more particularly, etching nitride selective to silicon dioxide or silicide, are disclosed. The methods include exposing a substrate having silicon nitride thereon to a plasma including at least one fluorohydrocarbon and a non-carbon containing fluorine source such as sulfur hexafluoride (SF6). The plasma may also include oxygen (O2) and the fluorohydrocarbons may include at least one of: trifluoromethane (CHF3), difluoromethane (CH2F2), and methyl fluoride (CH3F). In an alternative embodiment, the plasma includes one of hydrogen (H2) and nitrogen trifluoride (NF3) and one of tetrafluoromethane (CF4) and octafluorocyclobutane (C4F8). The methods are preferably carried out using a low bias voltage, e.g. <100 V.Type: ApplicationFiled: May 4, 2005Publication date: November 9, 2006Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC.Inventors: Siddhartha Panda, Richard Wise, Srikanteswara Murthy, Kamatchi Subramanian