Abstract: A method for secure key exchange. The method comprises receiving a request to certify a key from a communication partner at an interface between an access and tamper resistant circuit block and exposed circuitry. Within the access and tamper resistant circuit block, a first random private key is generated. A corresponding public key of the first random private key is derived, and a cryptographic digest of the public key and attributes associated with the first random private key is generated. The generated cryptographic digest is signed using a second random private key that has been designated for signing by one or more associated attributes. The public key and the signature are then sent to the communication partner via the interface.

Abstract: A method for secure key exchange. The method comprises receiving a request to certify a key from a communication partner at an interface between an access and tamper resistant circuit block and exposed circuitry. Within the access and tamper resistant circuit block, a first random private key is generated. A corresponding public key of the first random private key is derived, and a cryptographic digest of the public key and attributes associated with the first random private key is generated. The generated cryptographic digest is signed using a second random private key that has been designated for signing by one or more associated attributes. The public key and the signature are then sent to the communication partner via the interface.

Abstract: The present disclosure relates to systems for generating network packets that facilitate reliable and secure transmission of data between computing devices. For example, systems described herein involve generating a network packet in which a transport layer and security layer are implemented within an authentication header of the network packet. Information from the authentication header may be evaluated by a receiving device using a security key to compute an integrity check vector and an initialization vector to determine that a network packet has been provided in a correct order as well as check against a variety of security threats.

Abstract: A method for secure key exchange. The method comprises receiving a request to certify a key from a communication partner at an interface between an access and tamper resistant circuit block and exposed circuitry. Within the access and tamper resistant circuit block, a first random private key is generated. A corresponding public key of the first random private key is derived, and a cryptographic digest of the public key and attributes associated with the first random private key is generated. The generated cryptographic digest is signed using a second random private key that has been designated for signing by one or more associated attributes. The public key and the signature are then sent to the communication partner via the interface.

Abstract: Disclosed is a cryptographic key management system implemented in access and tamper resistant circuitry. The circuitry includes processing circuitry to perform cryptographic processing based cryptographic keys. Cryptographic key registers include key portions and attribute portions. An interface receives commands from exposed circuitry that controls the processing circuitry to perform cryptographic processing based on the keys and associated attributes. The attributes indicate what operations may be performed on, or using, the associated keys. of the associated keys. The attributes indicate intended uses of the keys.

Abstract: Disclosed is a cryptographic key management system implemented in access and tamper resistant circuitry. The circuitry includes processing circuitry to perform cryptographic processing based cryptographic keys. Cryptographic key registers include key portions and attribute portions. An interface receives commands from exposed circuitry that controls the processing circuitry to perform cryptographic processing based on the keys and associated attributes. The attributes indicate what operations may be performed on, or using, the associated keys. of the associated keys. The attributes indicate intended uses of the keys.

Abstract: A mesh grid protection system is provided. The system includes assertion logic configured to transmit a first set of signals on a first set of grid lines and a second set of grid lines. The system also includes transformation logic to transform the first set of signals to generate a second set of signals, to transmit the second set of signals on a third set of grid lines that are coupled to the first set of grid lines, and to transmit the second set of signals on a fourth set of grid lines that are coupled to the second set of grid lines. In addition, the system includes verification logic to compare the second set of signals on the third and fourth set of grid lines to an expected set of signals.

Abstract: RFID readers transmit a Quiet Technology (QT) command to RFID tags causing at least one of the tags to transition between a private profile and a public profile. When a tag is inventoried in the private profile, it replies to the reader with contents from its private memory. When a tag is inventoried in the public profile, it replies to the reader with contents from its public memory, where the contents of the public memory may be a subset and/or modified version of the private memory contents, or entirely different altogether. The tag's profile can be switched again by another QT command from the reader, or following a loss of power at the tag. An access password and/or a short-range mechanism may be employed to allow only authorized readers to transition tag profiles or interrogate the private memory contents of tags in the public profile.

Abstract: A mesh grid protection system is provided. The system includes assertion logic configured to transmit a first set of signals on a first set of grid lines and a second set of grid lines. The system also includes transformation logic to transform the first set of signals to generate a second set of signals, to transmit the second set of signals on a third set of grid lines that are coupled to the first set of grid lines, and to transmit the second set of signals on a fourth set of grid lines that are coupled to the second set of grid lines. In addition, the system includes verification logic to compare the second set of signals on the third and fourth set of grid lines to an expected set of signals.

Abstract: A mesh grid protection system is provided. The system includes assertion logic configured to transmit a first set of signals on a first set of grid lines and a second set of grid lines. The system also includes transformation logic to transform the first set of signals to generate a second set of signals, to transmit the second set of signals on a third set of grid lines that are coupled to the first set of grid lines, and to transmit the second set of signals on a fourth set of grid lines that are coupled to the second set of grid lines. In addition, the system includes verification logic to compare the second set of signals on the third and fourth set of grid lines to an expected set of signals.

Abstract: RFID readers transmit a Quiet Technology (QT) command to RFID tags causing at least one of the tags to transition between a private profile and a public profile. When a tag is inventoried in the private profile, it replies to the reader with contents from its private memory. When a tag is inventoried in the public profile, it replies to the reader with contents from its public memory, where the contents of the public memory may be a subset and/or modified version of the private memory contents, or entirely different altogether. The tag's profile can be switched again by another QT command from the reader, or following a loss of power at the tag. An access password and/or a short-range mechanism may be employed to allow only authorized readers to transition tag profiles or interrogate the private memory contents of tags in the public profile.

Abstract: A mesh grid protection system is provided. The system includes assertion logic configured to transmit a first set of signals on a first set of grid lines and a second set of grid. lines. The system also includes transformation logic to transform the first set of signals to generate a second set of signals, to transmit the second set of signals on a third set of grid lines that are coupled to the first set of grid lines, and to transmit the second set of signals on a fourth set of grid lines that are coupled to the second set of grid lines. In addition, the system includes verification logic; to compare the second set of signals on the third and fourth set of grid lines to an expected set of signals.

Abstract: A mesh grid protection system is provided. The system includes grid lines forming a mesh grid proximate to operational logic and assertion logic configured to transmit a first set of signals on a first set of grid lines. The system also includes transformation logic coupled to the grid lines and configured to receive the first set of signals and transform the first set of signals to generate a second set of signals and transmit the second set of signals on a second set of grid lines. The system further includes verification logic coupled to the transformation logic and configured to compare the second set of signals to an expected set of signals.

Abstract: A mesh grid protection system is provided. The system includes grid lines forming a mesh grid proximate to operational logic and assertion logic configured to transmit a first set of signals on a first set of grid lines. The system also includes transformation logic coupled to the grid lines and configured to receive the first set of signals and transform the first set of signals to generate a second set of signals and transmit the second set of signals on a second set of grid lines. The system further includes verification logic coupled to the transformation logic and configured to compare the second set of signals to an expected set of signals.

Abstract: RFID tags, ICs for RFID tags, and methods are provided. In some embodiments, an RFID tag includes a memory with multiple sections, and a processing block. The processing block may map one of these sections, or another of these sections, for purposes of responding to a first command from an RFID reader. As such, an RFID tag can operate according to the data stored in the section mapped at the time. In some embodiments, a tag can even transition from mapping one of the sections to mapping another of the sections. This can amount to the tag exhibiting alternative behaviors, and permits hiding data on the tag.

Abstract: RFID readers transmit a Quiet Technology (QT) command to RFID tags causing at least one of the tags to transition between a private profile and a public profile. When a tag is inventoried in the private profile, it replies to the reader with contents from its private memory. When a tag is inventoried in the public profile, it replies to the reader with contents from its public memory, where the contents of the public memory may be a subset and/or modified version of the private memory contents, or entirely different altogether. The tag's profile can be switched again by another QT command from the reader, or following a loss of power at the tag. An access password and/or a short-range mechanism may be employed to allow only authorized readers to transition tag profiles or interrogate the private memory contents of tags in the public profile.

Abstract: A method of adjusting operation of an RFID tag for an environment is described. The method includes sensing an aspect of the environment. The method also includes sending an instruction, based on the sensed aspect of the environment, to the RFID tag. The instruction encoded in a TUNE command. The instruction causes the RFID tag to perform a specific act. The specific act includes one of the following: turning a sub-circuit of the RFID tag's semiconductor chip on; turning a sub-circuit of the RFID tag's semiconductor chip off; altering a bias current within a sub-circuit of the RFID tag's semiconductor chip; altering a bias voltage within a sub-circuit of the RFID tag's semiconductor chip; and, adjusting a threshold within a sub-circuit of the RFID tag's semiconductor chip.

Abstract: RFID tags and chips for RFID tags are capable of being inventoried in one or more early attempts. These tags are capable of then refraining from participating in one or more subsequent inventorying attempts. In some embodiments refraining is performed solely by the tag, while in others it is guided by the RFID reader. In some embodiments, an inventoried indicator in the tag becomes updated upon backscattering. The updated value is used by the tag to recognize a subsequent attempt, and thus refrain from participating in it. This permits the subsequent attempt to be used more intensively for inventorying the more elusive, harder-to-read tags, especially in more demanding scenarios.

Abstract: RFID tags, ICs for RFID tags, and methods are provided. In some embodiments, an RFID tag includes a memory with multiple sections, and a processing block. The processing block may map one of these sections, or another of these sections, for purposes of responding to a first command from an RFID reader. As such, an RFID tag can operate according to the data stored in the section mapped at the time. In some embodiments, a tag can even transition from mapping one of the sections to mapping another of the sections. This can amount to the tag exhibiting alternative behaviors, and permits hiding data on the tag.

Abstract: A semiconductor chip for an RFID tag is described. The semiconductor chip including wireless transceiver and processing block circuitry to receive and put into effect a wirelessly received instruction encoded in a TUNE command. The instruction commanding the semiconductor chip to perform at least one specific act. The semiconductor chip having circuitry to perform the at least one specific act. The circuitry being coupled to the processing block. The circuitry and its corresponding specific act identified by at least one of the following: enablement circuitry to turn a sub-circuit within the semiconductor chip on; disablement circuitry to turn a sub-circuit within the semiconductor chip off; current bias circuitry to alter a bias current within a sub-circuit of the semiconductor chip; voltage bias circuitry to alter a bias voltage within a sub-circuit of the semiconductor chip; threshold adjustment circuitry to adjust a threshold within a sub-circuit of the semiconductor chip.