Abstract: A system that includes a graphical user interface (GUI) connected to an input/output device of a computer system and one or more test instruments producing a set of electrical signals. The system also includes a probe card that has a multiple probe needles used for measuring electronic characteristics of each of the devices on a semiconductor wafer. Each device has cells. Each cell has a set of bond pads. The system also has a matrix switch and an interface conduit electrically connecting the one or more test instruments, the computer, the probe card, and the matrix switch together. The semiconductor wafer is moved so that the probe needles measure the electrical characteristics of each cell for each device selected for testing.

Abstract: A system includes a multi-sided module having a cavity housing a substrate and n photoreceivers located on a side of the substrate and adapted to receive a beam of collimated light directed by a waveguide. The system also includes an integrated circuit (IC) positioned at the substrate to receive output from the photoreceiver.

Abstract: A system that includes a graphical user interface (GUI) connected to an input/output device of a computer system and one or more test instruments producing a set of electrical signals. The system also includes a probe card that has a multiple probe needles used for measuring electronic characteristics of each of the devices on a semiconductor wafer. Each device has cells. Each cell has a set of bond pads. The system also has a matrix switch and an interface conduit electrically connecting the one or more test instruments, the computer, the probe card, and the matrix switch together. The semiconductor wafer is moved so that the probe needles measure the electrical characteristics of each cell for each device selected for testing.

Abstract: A system includes a multi-sided module having a cavity housing a substrate and n photoreceivers located on a side of the substrate and adapted to receive a beam of collimated light directed by a waveguide. The system also includes an integrated circuit (IC) positioned at the substrate to receive output from the photoreceiver.

Abstract: The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15′) above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15′) in order to uncover the surface of the first insulating layer (25); forming a contact (11a′) in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15′); and providing an interconnect (40a) for electrical connecti

Abstract: The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15′) above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15′) in order to uncover the surface of the first insulating layer (25); forming a contact (11a′) in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15′); and providing an interconnect (40a) for electrical connecti

Abstract: A circuit configuration is described that has a first voltage terminal, a second voltage terminal and a control input. A reference-ground potential is applied to the first voltage terminal and an operating voltage is applied to the second voltage terminal. The control input is supplied with a control voltage, the control voltage assumes voltage values which alternate between the reference-ground potential and the operating voltage. The alternation of the control voltage has the effect that components such as transistors and inverter that are present in the circuit configuration are active and thereby experience an accelerated aging process in order to stabilize the threshold voltage of the MOS transistor.

Abstract: A circuit configuration is described that has a first voltage terminal, a second voltage terminal and a control input. A reference-ground potential is applied to the first voltage terminal and an operating voltage is applied to the second voltage terminal. The control input is supplied with a control voltage, the control voltage assumes voltage values which alternate between the reference-ground potential and the operating voltage. The alternation of the control voltage has the effect that components such as transistors and inverter that are present in the circuit configuration are active and thereby experience an accelerated aging process.

Abstract: The invention relates to a fast signal selector having a plurality of transfer gates which are connected in parallel. The input signals are applied to the signal inputs of the transfer gates and a selection signal is applied to control inputs of the transfer gates. Due to the switching properties of the transfer gates, the input signals can be switched through onto a common output line essentially without any power loss and with a very short time delay of approximately 20 ps.