Abstract: A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer by implanting silicon atoms into the insulating layer. Further, a plurality of different conductive regions can be formed in the insulating layer. An electrical device such as a transistor or a diode can then be formed in each of the conductive regions. Because the conductive regions are formed in a conductive region which is largely electrically isolated from other conductive regions there is little possibility for adjacent devices to cause interference.

Abstract: A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer by implanting silicon atoms into the insulating layer. Further, a plurality of different conductive regions can be formed in the insulating layer. An electrical device such as a transistor or a diode can then be formed in each of the conductive regions. Because the conductive regions are formed in a conductive region which is largely electrically isolated from other conductive regions there is little possibility for adjacent devices to cause interference.

Abstract: Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. An upper buried region of a selected conductivity type is situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. Another upper buried region of opposite conductivity type to the first-mentioned upper buried region is preferably situated along the upper semiconductor interface. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate.

Abstract: Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricatable from a semiconductor structure having two levels of buried regions. In a typical embodiment lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. Upper buried regions of opposite conductivity type are similarly situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is normally configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.