Patents by Inventor Kameshwar Yadavalli

Kameshwar Yadavalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11538963
    Abstract: A multilayer light emitting device having a plurality of low Si—H bonding dielectric layers is disclosed for improved p-GaN contact performance. Improved p-side contact resistance is provided using one or more bonding, via or passivation layers in a multilayer light emitting structure by the use of processes and dielectric materials and precursors that provide dielectric layers with a hydrogen content of less than 13 at. %.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: December 27, 2022
    Assignee: Ostendo Technologies, Inc.
    Inventors: Kameshwar Yadavalli, JeongHyuk Park, Gregory Batinica, Andrew Teren, Clarence Crouch, Qian Fan, Hussein S. El-Ghoroury
  • Patent number: 11495714
    Abstract: Solid state light emitting micropixels array structures having hydrogen barrier layers to minimize or eliminate undesirable passivation of doped GaN structures due to hydrogen diffusion.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: November 8, 2022
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein El-Ghoroury, Kameshwar Yadavalli, Andrew Teren, Qian Fan
  • Patent number: 11476390
    Abstract: A III-V light emitting device with pixels (mesa regions) specifically designed to enable lower cost through layer vias is disclosed for reduced cost of manufacture of the device. Reduction of cost of manufacture is achieved by having non-uniform width trench regions formed during pixel etch for the multi-pixel array part of the device. Through-layer vias are specifically formed in the wider part of the trench regions using cheaper lithography toolset enabled by the larger via critical dimension achievable in the wider part of the trench regions (as compared to narrow part of the trench regions). Larger via critical dimension enables improved electrical (and consequently optical) performance of the device due to better overlay control as well as lower via resistance.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: October 18, 2022
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Qian Fan, Kameshwar Yadavalli
  • Publication number: 20220090266
    Abstract: Solid state light emitting micropixels array structures having hydrogen barrier layers to minimize or eliminate undesirable passivation of doped GaN structures due to hydrogen diffusion.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 24, 2022
    Applicant: Ostendo Technologies, Inc.
    Inventors: Hussein El-Ghoroury, Kameshwar Yadavalli, Andrew Teren, Qian Fan
  • Patent number: 11195975
    Abstract: Solid state light emitting micropixels array structures having hydrogen barrier layers to minimize or eliminate undesirable passivation of doped GaN structures due to hydrogen diffusion.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: December 7, 2021
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Kameshwar Yadavalli, Andrew Teren, Qian Fan
  • Publication number: 20210242372
    Abstract: A III-V light emitting device with pixels (mesa regions) specifically designed to enable lower cost through layer vias is disclosed for reduced cost of manufacture of the device. Reduction of cost of manufacture is achieved by having non-uniform width trench regions formed during pixel etch for the multi-pixel array part of the device. Through-layer vias are specifically formed in the wider part of the trench regions using cheaper lithography toolset enabled by the larger via critical dimension achievable in the wider part of the trench regions (as compared to narrow part of the trench regions). Larger via critical dimension enables improved electrical (and consequently optical) performance of the device due to better overlay control as well as lower via resistance.
    Type: Application
    Filed: January 28, 2021
    Publication date: August 5, 2021
    Inventors: Hussein S. El-Ghoroury, Qian Fan, Kameshwar Yadavalli
  • Publication number: 20190378957
    Abstract: Solid state light emitting micropixels array structures having hydrogen barrier layers to minimize or eliminate undesirable passivation of doped GaN structures due to hydrogen diffusion.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 12, 2019
    Inventors: Hussein S. El-Ghoroury, Kameshwar Yadavalli, Andrew Teren, Qian Fan
  • Patent number: 10373830
    Abstract: An electromagnetic wave irradiation apparatus and methods to bond unbonded areas in a bonded pair of substrates are disclosed. The unbonded areas between the substrates are eliminated by thermal activation in the unbonded areas induced by electromagnetic wave irradiation having a wavelength selected to effect a phonon or electron excitation. A first substrate of the bonded pair of substrates absorbs the electromagnetic radiation and a portion of a resulting thermal energy transfers to an interface of the bonded pair of substrates at the unbonded areas with sufficient flux to cause opposite sides the first and second substrates to interact and dehydrate to form a bond (e.g., Si—O—Si bond).
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: August 6, 2019
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Minghsuan Liu, Kameshwar Yadavalli, Weilong Tang, Benjamin A. Haskell, Hailong Zhou
  • Patent number: 9978582
    Abstract: A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: May 22, 2018
    Assignee: Ostendo Technologies, Inc.
    Inventors: Gregory Batinica, Kameshwar Yadavalli, Qian Fan, Benjamin A. Haskell, Hussein S. El-Ghoroury
  • Publication number: 20170263457
    Abstract: An electromagnetic wave irradiation apparatus and methods to bond unbonded areas in a bonded pair of substrates are disclosed. The unbonded areas between the substrates are eliminated by thermal activation in the unbonded areas induced by electromagnetic wave irradiation having a wavelength selected to effect a phonon or electron excitation. A first substrate of the bonded pair of substrates absorbs the electromagnetic radiation and a portion of a resulting thermal energy transfers to an interface of the bonded pair of substrates at the unbonded areas with sufficient flux to cause opposite sides the first and second substrates to interact and dehydrate to form a bond (e.g., Si—O—Si bond).
    Type: Application
    Filed: March 7, 2017
    Publication date: September 14, 2017
    Inventors: Hussein S. El-Ghoroury, Minghsuan Liu, Kameshwar Yadavalli, Weilong Tang, Benjamin A. Haskell, Hailong Zhou
  • Publication number: 20170178891
    Abstract: A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 22, 2017
    Inventors: Gregory Batinica, Kameshwar Yadavalli, Qian Fan, Benjamin A. Haskell, Hussein S. El-Ghoroury
  • Patent number: 9306116
    Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface by interfusing optical interconnects on one wafer with optical interconnects on a second wafer, interfusing electrical interconnects on one wafer with electrical interconnects on the second wafer, and interfusing a dielectric intermediary bonding layer on one wafer with the dielectric intermediary bonding layer on the second wafer to bond the wafers together with electrical interconnections and optical interconnections between the wafers. The methods are also applicable to the bonding of semiconductor wafers to provide a high density of electrical interconnects between wafers.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: April 5, 2016
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Chih-Li Chuang, Kameshwar Yadavalli, Qian Fan
  • Publication number: 20150072450
    Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods for bonding of semiconductor wafers incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed across the bonding surface using multiplicity of metal posts each comprised of multiple layers of metal that are interfused across the bonding surface. The optical vias are formed across the bonding surface using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers.
    Type: Application
    Filed: November 10, 2014
    Publication date: March 12, 2015
    Inventors: Hussein S. El-Ghoroury, Chih-Li Chuang, Kameshwar Yadavalli, Qian Fan
  • Patent number: 8912017
    Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed using multiplicity of metal posts each comprised of multiple layers of metal that are interfused across the bonding surface. The optical vias are formed using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers. The electrical and optical vias are interspersed across the bonding surface between the bonded wafers to enable uniform transfer of both electrical and optical signals between the bonded wafers.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: December 16, 2014
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Chih-Li Chuang, Kameshwar Yadavalli, Qian Fan
  • Publication number: 20120288995
    Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed across the bonding surface using multiplicity of metal posts that are interfused across the bonding surface. The optical vias are formed across the bonding surface using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers. The electrical and optical vias are interspersed across the bonding surface between the bonded wafers to enable uniform transfer of both electrical and optical signals between the bonded wafers.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 15, 2012
    Applicant: OSTENDO TECHNOLOGIES, INC.
    Inventors: Hussein S. El-Ghoroury, Chih-Li Chuang, Kameshwar Yadavalli, Qian Fan