Abstract: Techniques for region-aware memory bandwidth allocation control are described. In an embodiment, an apparatus includes a processing core and control circuitry. The processing core is to execute a plurality of threads. The control circuitry is to control use of memory bandwidth per memory region and per thread.

Abstract: Techniques for allowing a control and/or status register to be read or written to in a user privilege level are described. An example of an instruction for user privilege read is to include one or more fields for an opcode, one or more fields for a source operand that is to store a control and/or status register address, and one or more fields for a destination register operand, wherein the opcode is to indicate that execution circuitry is to read data from the control and/or status register whose identity is stored in the source operand and write the data in the destination register operand responsive to access to the control and/or status register being allowed, wherein access to the control and/or status register is at least in part determined by data of an operating system controlled data structure indexed by the control and/or status register address.

Abstract: Techniques for providing and using a 32-bit immediate in an instruction are described. In some examples, an instance of a single instruction is to include one or more fields for an opcode, one or more fields for one or more operands, one or more fields for a prefix, and a field for an immediate value, wherein the opcode is to indicate one or more operations to be performed using the operands and the prefix is to indicate support for use of the immediate value during execution of the instance of the single instruction.

Abstract: An embodiment of an integrated circuit may comprise a prefetcher, a model specific register that is accessible at runtime to store information associated with the prefetcher, and circuitry communicatively coupled to the model specific register and prefetcher to adjust a runtime operation of the prefetcher based on the information associated with the prefetcher stored in the model specific register. Other embodiments are disclosed and claimed.

Abstract: Methods and apparatus relating to issue, execution, and backend driven frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input, and generates one or more outputs based at least in part on the static input and the dynamic input. The DTL circuitry generates the one or more outputs prior to commencement of speculation operations in a processor. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input and generates one or more outputs based at least in part on the static input and the dynamic input. A frontend counter generates a count value for the dynamic input based at least in part on an incremented/decremented counter value and a next counter value from the DTL circuitry. The DTL circuitry is capable to receive a new dynamic input prior to consumption of the one or more outputs. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, a processor includes: a plurality of registers; a front end circuit to fetch and decode a non-serializing register write instruction, the non-serializing register write instruction to cause a value to be stored in a first register of the plurality of registers; and an execution circuit coupled to the front end circuit. The execution circuit, in response to the non-serializing register write instruction, is to determine an amount of serialization for the non-serializing register write instruction and execute the non-serializing register write instruction according to the amount of serialization. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes: a front end circuit to fetch and decode a read list instruction, the read list instruction to cause storage to a memory of a software-provided list of processor state information; and an execution circuit coupled to the front end circuit. The execution circuit, in response to the decoded read list instruction, is to read the processor state information stored in the processor and store each datum of the processor state information into an entry of a data table in the memory. Other embodiments are described and claimed.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement a cross-lane packed data instruction on a partial (e.g., half) width processor with a minimal number of micro-operations are described. In one embodiment, a hardware processor core includes a decoder circuit to decode a single packed data instruction into only a first micro-operation and a second micro-operation, a packed data execution circuit to execute the first micro-operation and the second micro-operation, and a reservation station circuit coupled between the decoder circuit and the packed data execution circuit, the reservation station circuit comprising a first reservation station entry for the first micro-operation to store a first set of fields that indicate three or more input sources and a first destination, and a second reservation station entry for the second micro-operation to store a second set of fields to indicate three or more input sources and a second destination.

Abstract: In one embodiment, software executing on a data processing system that is capable of performing dynamic operational mode transitions can realize performance improvements by predicting transitions between modes and/or predicting aspects of a new operational mode. Such prediction can allow the processor to begin an early transition into the target mode. The mode transition prediction principles can be applied for various processor mode transitions including 64-bit to 32-bit mode transitions, interrupts, exceptions, traps, virtualization mode transfers, system management mode transfers, and/or secure execution mode transfers.

Abstract: In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback indicator to indicate to an operating system (OS) that the processor is to provide hardware feedback information to the OS dynamically and a power controller coupled to the plurality of cores. The power controller may include a feedback control circuit to dynamically determine the hardware feedback information for at least one of the plurality of cores and inform the OS of an update to the hardware feedback information. Other embodiments are described and claimed.

Abstract: Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.

Abstract: In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback indicator to indicate to an operating system (OS) that the processor is to provide hardware feedback information to the OS dynamically and a power controller coupled to the plurality of cores. The power controller may include a feedback control circuit to dynamically determine the hardware feedback information for at least one of the plurality of cores and inform the OS of an update to the hardware feedback information. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.

Abstract: In one embodiment, software executing on a data processing system that is capable of performing dynamic operational mode transitions can realize performance improvements by predicting transitions between modes and/or predicting aspects of a new operational mode. Such prediction can allow the processor to begin an early transition into the target mode. The mode transition prediction principles can be applied for various processor mode transitions including 64-bit to 32-bit mode transitions, interrupts, exceptions, traps, virtualization mode transfers, system management mode transfers, and/or secure execution mode transfers.

Abstract: A processor includes a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine. The processor further includes a first microcode alias storage comprising a first plurality of microcode alias locations and a second microcode alias storage comprising a second plurality of microcode alias locations. The processor further includes a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is configured to select a first one of a) the first microcode alias storage for storage of a parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the parameter location in one of the second plurality of microcode alias locations.

Abstract: An apparatus including an execution logic that includes circuitry to execute instructions, and an instruction execution scheduler logic coupled with the execution logic. The instruction execution scheduler logic is to receive an execute at commit state update instruction. The instruction execution scheduler logic includes at commit state update logic that is to wait to schedule the execute at commit state update instruction for execution until the execute at commit state update instruction is a next instruction to commit. Other apparatus, methods, and systems are also disclosed.

Abstract: A processor includes a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine. The processor further includes a first microcode alias storage comprising a first plurality of microcode alias locations and a second microcode alias storage comprising a second plurality of microcode alias locations. The processor further includes a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is configured to select a first one of a) the first microcode alias storage for storage of a parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the parameter location in one of the second plurality of microcode alias locations.

Abstract: Methods and apparatus for enhanced microcode address stack pointer manipulation are described. In some examples, the stacks are invisible to software. A microcode instruction pointer (UIP) and a next address to be accessed in a microcode storage unit may be generated based on an opcode of a microoperation, a marker, and a UIP stack address. The UIP stack address may be generated based on a signal and an immediate field of the microoperation.