Abstract: A system and method for ADSL USB bandwidth negotiation are presented. The system comprises a modem that is configured to transfer data between an ADSL line and a USB bus and that is further configured to receive an ADSL line rate setting, submit an isochronous bandwidth request to a computer, reduce the isochronous bandwidth request in response to the availability of isochronous bandwidth, modify the ADSL line rate setting in response to the availability of isochronous bandwidth, and modify the USB bus transfer mode in response to the availability of isochronous bandwidth. The method comprises steps of receiving an ADSL line rate setting, submitting an isochronous bandwidth request to a computer, reducing the isochronous bandwidth request in response to the availability of isochronous bandwidth, modifying the ADSL line rate setting in response to the availability of isochronous bandwidth, and modifying the USB bus transfer mode of the ADSL USB modem in response to the availability of isochronous bandwidth.

Abstract: A computer system includes bridge logic that couples peripheral devices to a CPU and main memory and includes power management logic and a programmable interrupt controller. The power management logic includes control logic, a stop clock register, an alternate stop clock register, and a wakeup event register. The operating system initiates a transition to a lower power mode of operation by issuing an IDLE call to the BIOS which responds by configuring a modulation value of 15 into the alternate stop clock register. With a modulation value of 15, the SLEEPREQ signal is continuously asserted disabling the CPU's internal clock. When a subsequent wakeup event occur, an enable bit in the alternate stop clock register is cleared, disabling modulation and deasserting SLEEPREQ. In response to the wakeup event, the amount of SLEEPEQ modulation is changed. Preferably the modulation value is changed to 14 so that SLEEPREQ is asserted for 14 out of every 15 cycles of a 32 KHz clock.

Abstract: A computer system in which various system peripherals are automatically re-initialized after being hot-swapped. The reinitialization includes accommodation of any required master/slave relationships between the peripherals.