Abstract: A method includes forming a first transistor over a substrate, in which the first transistor includes first source/drain epitaxy structures; forming a second transistor over the first transistor, in which the second transistor includes second source/drain epitaxy structures; forming an opening extending through one of the second source/drain epitaxy structures and exposing a top surface of one of the first source/drain epitaxy structures; performing a first deposition process to form a first metal in the opening, in which a first void is formed in the first metal during the first deposition process; performing a first etching back process to the first metal until the first void is absent; and performing a second deposition process to form a second metal in the opening and over the first metal.

Abstract: A semiconductor device that has two transistors and a source/drain contact. The first transistor has a layer of semiconductor material that acts as a channel, a structure that serves as a gate and wraps around the semiconductor channel layer, and two epitaxy structures on either end of the semiconductor channel layer that function as the source and drain. The second transistor is situated above the first transistor and has similar components, including a semiconductor channel layer, gate structure, and source/drain epitaxy structures. The connection between the first and second source/drain epitaxy structures is made by a source/drain contact that passes through one of the second source/drain epitaxy structures. This contact is made up of a metal plug and a metal liner that lines the plug.

Abstract: A computer-implemented method includes: placing and routing design elements in a simulation environment; applying one or more simulation conditions to the design elements; obtaining a first set of data based on the one or more simulation conditions, and a first relationship between the first set of data; obtaining a prediction model based on the first relationship; and predicting a new set of data using the prediction model.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: The present invention relates to a pharmaceutical composition containing liposomes, said liposome comprise an external lipid bilayer; and an internal aqueous medium including a weak acid drug with a half-life of less than 2 hours. Also provided is the use of the pharmaceutical composition disclosed herein to treat pulmonary hypertension with reduced dosing frequency.

Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.

Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.

Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.

Abstract: Disclosed herein are impedance-based biosensor systems comprising an impedance-based biosensor having an electrode, a meter in electrical communication with the electrode, a processor in electrical communication with the impedance-based biosensor and the meter, and a memory storing instructions to be executed by the processor. The instructions can cause the impedance-based biosensor system to measure the impedance of the electrode, derive one or more electrical properties of the impedance-based biosensor from the impedance of the electrode, and calculate a viable cell count based on the one or more electrical properties.

Abstract: Semiconductor structures and processes of forming the same are provided. A semiconductor structure according to the present disclosure includes a first bottom source/drain feature and a second bottom source/drain feature disposed over a substrate, a plurality of bottom channel members extending between and in contact with the first bottom source/drain feature and the second bottom source/drain feature, a first bonding layer over the plurality of bottom channel members, a second bonding layer disposed directly on the first bonding layer, a first top source/drain feature disposed directly over the first bottom source/drain feature, a second top source/drain feature disposed directly over the second bottom source/drain feature, and a plurality of top channel members disposed over the second bonding layer and extending between and in contact with the first top source/drain feature and the second top source/drain feature.

Abstract: A semiconductor structure includes a substrate having a first surface and a second surface opposite the first surface. The semiconductor structure includes a semiconductor device disposed on the first surface. The semiconductor structure includes a metallization layer disposed on the second surface. The semiconductor structure includes a first conductive via and a second conductive via coupled in parallel to the metallization layer, the first conductive via and the second conductive via extending from the second side toward the first side. The semiconductor structure further includes an electrical fuse disposed over the semiconductor device and coupled to the first and second conductive vias.

Abstract: A method includes forming a transistor layer; forming a first metallization layer, including: forming first conductors, aligned along alpha tracks, and representing input pins of a cell region including first and second input pins; and cutting lengths of the first and second input pins to accommodate at most two access points, each aligned to a different one of first to fourth beta tracks, the beta tracks to which are aligned the access points of the first input pin being different than the beta tracks to which are aligned the access points of the second input pin; and forming a second metallization layer, including: forming second conductors representing routing segments and a representing a power grid segment aligned with one of the beta tracks of access points of the first input pin or the access points of the second input pin.

Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.

Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.

Abstract: The present invention relates to a pharmaceutical composition containing liposomes, said liposome comprise an external lipid bilayer; and an internal aqueous medium including a weak acid drug with a half-life of less than 2 hours. Also provided is the use of the pharmaceutical composition disclosed herein to treat pulmonary hypertension with reduced dosing frequency.

Abstract: There is provided a method comprising receiving at least one measured signal characteristic from a user equipment, the user equipment being located at a user equipment location; comparing the at least one measured signal characteristic to at least one of a plurality of signal characteristics, each signal characteristic being associated with a respective measurement point; and determining, based on the comparing, a probability that the user equipment location is a first location.

Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.

Abstract: The present application relates to a transcatheter prosthetic valve replacement system including a delivery catheter, a frame, a prosthetic valve, and one or more clamping devices. The prosthetic valve is fixed in the frame. The clamping device is connected to a periphery of the frame. The frame and the clamping device can be preloaded in the delivery catheter. The clamping device includes a clamping member, a collar, and a control member. One end of the clamping member is a fixation end which is fixedly connected to the frame, and the other end of the clamping member is a deployable resilient segment which can be compressed and released. The collar is slidably sleeved on the clamping member. One end of the control member is connected to the collar, and the other end of the control member is manipulated outside the body. From being compressed to being fully released, the clamping member in sequence has two configurations.

Abstract: There is provided a method comprising receiving at least one measured signal characteristic from a user equipment, the user equipment being located at a user equipment location; comparing the at least one measured signal characteristic to at least one of a plurality of signal characteristics, each signal characteristic being associated with a respective measurement point; and determining, based on the comparing, a probability that the user equipment location is a first location.