Abstract: A fractional up-sampling filter is configured to convert a lower data rate to a higher data rate by using methods of interpolation to generate output digital data that corresponds to the higher data rate. For example, if the higher data rate output is 4/3 of the lower data rate input, then for every three (3) digital data values originally sampled by the fractional up-sampling filter, four (4) output digital data values are generated and output from the filter. These output digital data values are obtained by methods of interpolation. Interpolation is performed using different filter coefficients depending on the relative timing of the output digital data rate versus the original sampling rate. The fractional up-sampling filter utilizes a high frequency master clock to derive the fractional relationship between the original sampling rate to the new fractional sampling rate.

Abstract: A calibration circuit is configured to provide automatic feedback calibration during a tuning cycle. Automating the calibration process reduces the engineering evaluation time and mass production test time. The calibration settings vary as a function of frequency, and the calibration circuit automatically determines the proper calibration for any frequency application. The calibration circuit enhances communication performance by comparing and computing a time difference between a reference path and a feedback path. The calibration circuit is configured as part of a phase modulation path within a modulation circuit. The calibration circuit provides for calibration without prior knowledge of the system and reduced factory test time. The calibration circuit provides numerous advantages, including, but not limited to, accurate system results for time, frequency, temperature, and process variations with each calibration, or tuning.